公开(公告)号：US20060133129A1

公开(公告)日：2006-06-22

申请号：US11017572

申请日：2004-12-20

Applicant: John Rodriguez ,  K. Udayakumar

Inventor： John Rodriguez ,  K. Udayakumar

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: The present invention facilitates data retention lifetimes for ferroelectric devices by improving switched polarization of ferroelectric memory cells. A ferroelectric memory device comprising ferroelectric memory cells is provided (702). A duration for applying a DC bias to the ferroelectric memory cells is selected (704) according to at least a desired switched polarization improvement. A magnitude for applying the DC bias to the ferroelectric memory cells is also selected (706) according to at least the desired switched polarization improvement. Further, an elevated temperature is selected for applying the DC bias to the ferroelectric memory cells is also selected (708) according to at least the desired switched polarization improvement. Subsequently, the DC bias is applied to the ferroelectric memory cells (710), which activates one or more inactive domains within the ferroelectric memory cells and increases initial polarization values.

Abstract translation: 本发明通过改善铁电存储器单元的开关极化来促进强电介质器件的数据保留寿命。 提供了包括铁电存储单元的铁电存储器件（702）。 根据至少所需的开关极化改善来选择向铁电存储器单元施加DC偏压的持续时间（704）。 根据至少所需的开关极化改善，也选择用于将DC偏压施加到铁电存储单元的幅度（706）。 此外，根据至少所需的开关极化改善，还选择（708）将用于将DC偏压施加到铁电存储器单元的升高的温度。 随后，将DC偏压施加到铁电存储单元（710），其激活铁电存储单元内的一个或多个非活性区域并增加初始极化值。

公开(公告)号：US20050205906A1

公开(公告)日：2005-09-22

申请号：US10803445

申请日：2004-03-18

Applicant: K. Udayakumar ,  Theodore Moise ,  Scott Summerfelt

Inventor： K. Udayakumar ,  Theodore Moise ,  Scott Summerfelt

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/8246 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L27/11507 ,  H01L28/57

Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.

Abstract translation: 提供氢屏障和制造方法用于在半导体器件（102）中保护铁电电容器（C LIMIT）免受氢扩散，其中氮化的氧化铝（N-AlOx）形成在铁电电容器（C < 在氮化的氧化铝（N-AlOx）上形成一个或多个氮化硅层（112,117）。 还提供了氢屏障，其中在铁电电容器（CFE）上形成氧化铝（AlOx，N-AlOx），其上形成有两个或更多个氮化硅层（112,117） 氧化铝（AlOx，N-AlOx），其中第二氮化硅层（112）包括低硅氢SiN材料。

公开(公告)号：US20060073613A1

公开(公告)日：2006-04-06

申请号：US10952987

申请日：2004-09-29

Applicant: Sanjeev Aggarwal ,  K. Udayakumar ,  James Martin

Inventor： Sanjeev Aggarwal ,  K. Udayakumar ,  James Martin

IPC: H01L21/00 ,  H01L21/20 ,  H01L21/8242

CPC classification number: H01L28/57 ,  H01L27/11502 ,  H01L27/11507

Abstract: Methods (100) are provided for fabricating a ferroelectric capacitor in a semiconductor device wafer, comprising forming (118) a lower electrode, depositing (126) PZT ferroelectric material on the lower electrode at a temperature below 450 degrees C., and forming (128) an upper electrode on the PZT. Methods are also provided for fabricating a ferroelectric memory cell in a semiconductor device wafer, comprising forming (106) a transistor in the wafer, forming (108) a nickel silicide structure on the gate or a source/drain of the transistor, forming (110) a dielectric over the transistor, forming (112) a conductive contact extending through the dielectric to the silicide structure, forming (114, 116, 118, 120) a lower electrode on at least a portion of the conductive contact, forming (126) PZT ferroelectric material above and in contact with the lower electrode at a temperature below 450 degrees C., forming (128, 132) an upper electrode above and in contact with the PZT, and patterning (134) the upper electrode, the PZT, and the lower electrode to form a patterned ferroelectric capacitor.

Abstract translation: 提供了用于在半导体器件晶片中制造铁电电容器的方法（100），包括在低于450℃的温度下形成（118）下电极，在下电极上沉积（126）PZT铁电材料，以及形成（128 ）PZT上的上电极。 还提供了用于在半导体器件晶片中制造铁电存储单元的方法，包括在晶片中形成（106）晶体管，在晶体管的栅极或源极/漏极上形成（108）硅化镍结构，形成（110） ）在所述晶体管上形成电介质，形成（112）延伸穿过所述电介质到所述硅化物结构的导电接触，在所述导电接触的至少一部分上形成（114,116,118,120）下电极， PZT铁电体材料在低于450℃的温度下方与下电极接触，在PZT上方形成（128,132）上电极并与PZT接触，并且（134）上电极，PZT和 下电极形成图案化的铁电电容器。

公开(公告)号：US20060134808A1

公开(公告)日：2006-06-22

申请号：US11016400

申请日：2004-12-17

Applicant: Scott Summerfelt ,  Lindsey Hall ,  K. Udayakumar ,  Theodore Moise

Inventor： Scott Summerfelt ,  Lindsey Hall ,  K. Udayakumar ,  Theodore Moise

IPC: H01L21/00

CPC classification number: H01L21/0206 ,  H01L21/02071 ,  H01L28/55 ,  H01L28/57 ,  H01L28/65 ,  H01L28/75

Abstract: Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define a patterned ferroelectric capacitor structure, and etching (143, 206) a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing (144, 203) the patterned ferroelectric capacitor structure using a first ashing process, performing (145, 204) a wet clean process after the first ashing process, and ashing (146, 205) the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.

Abstract translation: 提供了用于制造铁电电容器结构的方法（100），其包括用于在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法（128）。 所述方法包括：上电极的蚀刻（140,200）部分，蚀刻（141,201）铁电材料和蚀刻（142,202）下电极以限定图案化的铁电电容器结构，以及蚀刻（143,206）a 部分下部电极扩散阻挡结构。 所述方法还包括使用第一灰化处理灰化（144,203）所述图案化的铁电电容器结构，在第一灰化过程之后执行（145,204）湿式清洁处理，以及使用所述图案化铁电电容器结构灰化（146,205） 在氧化环境中的高温下在湿式清洁工艺之后直接进行第二次灰化处理。

公开(公告)号：US20050012126A1

公开(公告)日：2005-01-20

申请号：US10620516

申请日：2003-07-16

Applicant: K. Udayakumar ,  Martin Albrecht ,  Theodore Moise ,  Scott Summerfelt ,  Sanjeev Aggarwal ,  Jeff Large

Inventor： K. Udayakumar ,  Martin Albrecht ,  Theodore Moise ,  Scott Summerfelt ,  Sanjeev Aggarwal ,  Jeff Large

IPC: H01L21/02 ,  H01L23/00 ,  H01L29/06 ,  H01L21/00 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072

CPC classification number: H01L28/57 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier comprises silicon rich silicon oxide or amorphous silicon, which can be used in combination with an aluminum oxide layer to inhibit diffusion of process-related hydrogen into the ferroelectric capacitor layer.

Abstract translation: 提出了半导体器件和制造方法，其中在铁电电容器上方设置氢气阻挡层，以防止在使用氢的后端制造工艺期间铁电材料的劣化。 氢势垒包括富硅氧化物或非晶硅，其可以与氧化铝层组合使用以抑制工艺相关氢扩散到铁电电容器层中。

公开(公告)号：US20050205911A1

公开(公告)日：2005-09-22

申请号：US11033224

申请日：2005-01-11

Applicant: K. Udayakumar ,  Theodore Moise ,  Scott Summerfelt

Inventor： K. Udayakumar ,  Theodore Moise ,  Scott Summerfelt

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/8246 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L27/11507 ,  H01L28/57

Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.

Abstract translation: 提供氢屏障和制造方法用于在半导体器件（102）中保护铁电电容器（C LIMIT）免受氢扩散，其中氮化的氧化铝（N-AlOx）形成在铁电电容器（C < 在氮化的氧化铝（N-AlOx）上形成一个或多个氮化硅层（112,117）。 还提供了氢屏障，其中在铁电电容器（CFE）上形成氧化铝（AlOx，N-AlOx），其上形成有两个或更多个氮化硅层（112,117） 氧化铝（AlOx，N-AlOx），其中第二氮化硅层（112）包括低硅氢SiN材料。

公开(公告)号：US20050032301A1

公开(公告)日：2005-02-10

申请号：US10635994

申请日：2003-08-07

Applicant: K. Udayakumar ,  Maritin Albrecht ,  Theodore Moise ,  Scott Summerfelt ,  Sarah Hartwig

Inventor： K. Udayakumar ,  Maritin Albrecht ,  Theodore Moise ,  Scott Summerfelt ,  Sarah Hartwig

IPC: H01L21/02 ,  H01L21/318 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/8242 ,  H01L21/31 ,  H01L21/00 ,  H01L21/469

CPC classification number: H01L21/76829 ,  H01L21/3185 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/57

Abstract: Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion into ferroelectric capacitors and into transistor gate dielectric interface areas. The barriers may be used as etch stop layers in various levels of the semiconductor device structure above and/or below the level at which the ferroelectric capacitors are formed so as to reduce the hydrogen related degradation of the switched polarization properties of the ferroelectric capacitors and to reduce negative bias temperature instability in the device transistors.

Abstract translation: 公开了半导体器件和制造方法，其中提供一个或多个低硅氢SiN栅极以阻止氢扩散到铁电电容器中并进入晶体管栅极电介质界面区域。 可以将阻挡层用作在形成强电介质电容器的电平以上和/或以下的半导体器件结构的各种级别的蚀刻停止层，以便降低铁电电容器的开关极化特性的氢相关劣化，并且 降低器件晶体管的负偏压温度不稳定性。