公开(公告)号：US07069421B1

公开(公告)日：2006-06-27

申请号：US09429094

申请日：1999-10-28

申请人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Korbin S. Van Dyke ,  T. R. Ramesh

发明人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Korbin S. Van Dyke ,  T. R. Ramesh

IPC分类号： G06F9/30

CPC分类号： G06F9/45533

摘要： A microprocessor chip, and methods for use in that microprocessor chip. The chip has instruction pipeline circuitry and address translation circuitry. Table lookup circuitry indexes into a table, the table having an entry associated with each corresponding address range translated by the address translation circuitry. Each entry of the table describes a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range. The table lookup circuitry retrieves a table entry corresponding to the address, and is operable as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program executing on a computer. Interrupt circuitry is cooperatively designed with the instruction pipeline circuitry to trigger an interrupt on execution of an instruction of a process, synchronously based at least in part on a memory state of the computer and the address of the instruction, the architectural definition of the instruction not calling for an interrupt. A handler for the interrupt is responsive to the contents of the table to affect the instruction pipeline circuitry to effect control of an architecturally-visible data manipulation behavior or control transfer behavior of the instruction based on the contents of a table entry associated with the instruction.

摘要翻译： 微处理器芯片，以及用于该微处理器芯片的方法。 该芯片具有指令流水线电路和地址转换电路。 表查找电路索引到表中，该表具有与由地址转换电路翻译的每个相应地址范围相关联的条目。 该表的每个条目描述存在位于相应的相应地址范围内的指令的替代编码的可能性。 表查找电路检索对应于该地址的表条目，并可作为执行在计算机上执行的非主管模式程序的指令的基本指令周期的一部分。 中断电路与指令流水线电路协同设计，以至少部分地基于计算机的存储状态和指令的地址同步地触发执行过程指令的中断，指令的架构定义不是 要求中断。 用于中断的处理程序响应于表的内容，以影响指令流水线电路，以基于与该指令相关联的表条目的内容来实现对结构上可视数据操纵行为的控制或指令的控制传递行为。

公开(公告)号：US06826748B1

公开(公告)日：2004-11-30

申请号：US09339749

申请日：1999-06-24

申请人： Paul H. Hohensee ,  David L. Reese ,  John S. Yates, Jr. ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Niteen Aravind Patkar

发明人： Paul H. Hohensee ,  David L. Reese ,  John S. Yates, Jr. ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Niteen Aravind Patkar

IPC分类号： G06F944

CPC分类号： G06F9/45558 ,  G06F9/45541 ,  G06F9/45554 ,  G06F2009/45583

摘要： A method and computer for performance of the method. While executing a program on a computer, the computer uses registers of a general register file for storage of instruction results. Profile information describing the profileable events is recorded into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.

摘要翻译： 用于执行该方法的方法和计算机。 在计算机上执行程序时，计算机使用通用寄存器文件的寄存器来存储指令结果。 描述可概要事件的简档信息可记录在通用寄存器文件中，因为可以描述事件的发生，而无需先将信息捕获到计算机的主存储器中。

公开(公告)号：US06763452B1

公开(公告)日：2004-07-13

申请号：US09339797

申请日：1999-06-24

申请人： Paul H. Hohensee ,  John S. Yates, Jr. ,  Korbin S. Van Dyke ,  David L. Reese ,  Stephen C. Purcell

发明人： Paul H. Hohensee ,  John S. Yates, Jr. ,  Korbin S. Van Dyke ,  David L. Reese ,  Stephen C. Purcell

IPC分类号： G06F900

CPC分类号： G06F9/45558 ,  G06F9/45541 ,  G06F9/45554 ,  G06F2009/45583

摘要： A method and a multiprocessor computer for execution of the method. A first CPU has a general register file, an instruciton pipeline, and profile circuitry. The profile circuitry is operatively interconnected and under common hardware control with the instruction pipeline. The profile circuitry and instruction pipeline are cooperatively interconnected to detect the occurrence of profileable events occurring in the instruction pipeline. The profile circuitry is operable without software intervention to effect recording of profile information describing the profileable events into the general register file, without first capturing the information into a main memory of the computer. The recording is essentially concurrent with the occurrence of the profileable events. A second CPU is configured to analyze the generated profile data, while the execution and profile data generation continue on the first CPU, and to control the execution of the program on the first CPU based at least in part on the analysis of the collected profile data.

摘要翻译： 一种用于执行该方法的方法和多处理器计算机。 第一个CPU有一个通用寄存器文件，一个通道管道和一个轮廓电路。 配置文件电路与指令管道可操作地互连，并在通用的硬件控制下。 配置文件电路和指令流水线协同互连，以检测在指令流水线中发生的可轮廓事件的发生。 配置文件电路可操作而无需软件干预，以便将描述可描述事件的简档信息记录到通用寄存器文件中，而无需首先将信息捕获到计算机的主存储器中。 录音本质上与可配置事件的发生同时发生。 第二CPU被配置为分析生成的简档数据，同时在第一CPU上继续执行和简档数据生成，并且至少部分地基于所收集的简档数据的分析来控制第一CPU上的程序的执行 。

公开(公告)号：US20090204785A1

公开(公告)日：2009-08-13

申请号：US11982419

申请日：2007-10-31

申请人： John S. Yates, JR. ,  David L. Reese ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Paul H. Hohensee

发明人： John S. Yates, JR. ,  David L. Reese ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Paul H. Hohensee

IPC分类号： G06F9/30 ,  G06F12/10

CPC分类号： G06F9/30189 ,  G06F9/30174 ,  G06F9/30196 ,  G06F9/3802

摘要： A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture. or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.

摘要翻译： 一台电脑。 处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。 存储器存储由处理器流水线执行的指令，存储器被划分为页面以供虚拟存储器管理器管理，存储器的单个地址空间具有第一和第二页面。 存储器单元从存储器中取出指令以由流水线执行，并且获取存储的指示符元素，其与要获取指令的单个地址空间的相应存储器页相关联。 每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示，在该约定下，相关联的页面的指令数据将由处理器管线执行。 存储器单元和/或处理器流水线识别来自第一页面的执行流程，其相关联的指示符元素指示第一架构。 或执行约定，到第二页，其相关联的指示符元素指示第一个架构或执行约定。 响应于识别，处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。

公开(公告)号：US07013456B1

公开(公告)日：2006-03-14

申请号：US09334530

申请日：1999-06-16

申请人： Korbin S. Van Dyke ,  Paul H. Hohensee ,  David L. Reese ,  John S. Yates, Jr. ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Stephen C. Purcell ,  Niteen Aravind Patkar

发明人： Korbin S. Van Dyke ,  Paul H. Hohensee ,  David L. Reese ,  John S. Yates, Jr. ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Stephen C. Purcell ,  Niteen Aravind Patkar

IPC分类号： G06F9/44

CPC分类号： G06F9/45533 ,  G06F9/45541 ,  G06F9/45554

摘要： A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with the occurrence of the profileable events. The detecting and recording occur under control of hardware of the computer without software intervention.

摘要翻译： 一种用于执行该方法的方法和计算机。 在计算机上执行程序时，检测到在指令流水线中发生的可轮廓事件。 该指令流水线用于记录描述可概要事件的简档信息，基本上与可概要事件的发生同时发生。 检测和记录在没有软件干预的情况下在计算机硬件的控制下进行。

公开(公告)号：US08121828B2

公开(公告)日：2012-02-21

申请号：US11003768

申请日：2004-12-02

申请人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Stephen C. Purcell ,  Korbin S. Van Dyke

发明人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Stephen C. Purcell ,  Korbin S. Van Dyke

IPC分类号： G06F9/455

CPC分类号： G06F9/45533

摘要： A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

摘要翻译： 计算机具有能够执行两个指令集架构（ISA）的指令流水线电路。 二进制翻译器至少将计算机程序的选定部分从ISA的较低性能转换为ISA的更高性能的一个。 当即将执行在低性能ISA中编码的程序区域时，硬件启动查询，以确定是否存在更高性能的转换。 如果是这样，即将执行的指令被中止，并且控制转移到更高性能的转换。 执行较高性能的翻译后，在排除后的指令下游的一个点重新建立较低性能区域的执行，在逻辑上相当于在较低性能区域的代码被允许的情况下 继续。

公开(公告)号：US08065504B2

公开(公告)日：2011-11-22

申请号：US11004729

申请日：2004-12-02

申请人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Korbin S. Van Dyke ,  Shalesh Thusoo ,  Tiruvur R. Ramesh

发明人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Korbin S. Van Dyke ,  Shalesh Thusoo ,  Tiruvur R. Ramesh

IPC分类号： G06F9/30

CPC分类号： G06F9/45533

摘要： A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.

摘要翻译： 微处理器芯片具有指令流水线电路和指令分类电路，它们将执行的指令分类为少量类并记录分类代码值。 片上表具有对应于存储器的一系列地址的条目，并且被设计为保持在计算机的存储器中查看片外表的值的统计评估。 查找电路被设计为从微处理器的基本指令处理周期的一部分获取片上表格中的条目。 掩码至少部分由定时器设置的值。 基于与所处理的指令的地址，掩码的当前值，记录的分类代码和片外表相对应的片上表项的值来控制指令流水线电路。

公开(公告)号：US06789181B1

公开(公告)日：2004-09-07

申请号：US09432753

申请日：1999-11-03

申请人： John S. Yates ,  David L. Reese ,  Korbin S. Van Dyke ,  Paul H. Hohensee

发明人： John S. Yates ,  David L. Reese ,  Korbin S. Van Dyke ,  Paul H. Hohensee

IPC分类号： G06F944

CPC分类号： G06F9/45533

摘要： A method and computer for executing the method. A source program is translated into an object program, in a manner in which the translated object program has a different execution behavior than the source program. The translated object program is executed under a monitor capable of detecting any deviation from fully-correct interpretation before any side-effect of the different execution behavior is irreversibly committed. When the monitor detects the deviation, or when an interrupt occurs during execution of the object program, a state of the program is established corresponding to a state that would have occurred during an execution of the source program, and from which execution can continue. Execution of the source program continues primarily in a hardware emulator designed to execute instructions of an instruction set non-native to the computer.

摘要翻译： 一种用于执行该方法的方法和计算机。 源程序被翻译成对象程序，其中翻译的对象程序具有与源程序不同的执行行为。 在不可执行行为的任何副作用被不可逆转地提交之前，被翻译的对象程序在能够检测到完全正确解释的任何偏离的监视器下执行。 当监视器检测到偏差时，或者在执行对象程序期间发生中断时，根据在源程序执行期间发生的状态并且从哪个执行继续可以建立程序的状态。 源程序的执行主要在硬件仿真器中进行，该硬件仿真器旨在执行非本机的指令集的指令。

公开(公告)号：US08074055B1

公开(公告)日：2011-12-06

申请号：US09385394

申请日：1999-08-30

申请人： John S. Yates, Jr. ,  David L. Reese ,  Korbin S. Van Dyke ,  Tiruvur R. Ramesh ,  Paul H. Hohensee

发明人： John S. Yates, Jr. ,  David L. Reese ,  Korbin S. Van Dyke ,  Tiruvur R. Ramesh ,  Paul H. Hohensee

IPC分类号： G06F9/30

CPC分类号： G06F9/3005 ,  G06F9/30174 ,  G06F9/3804

摘要： A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.

摘要翻译： 一台电脑。 处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。 存储器存储由处理器流水线执行的指令，存储器被划分为页面以供虚拟存储器管理器管理，存储器的单个地址空间具有第一和第二页面。 存储器单元从存储器中取出指令以由流水线执行，并且获取存储的指示符元素，其与要获取指令的单个地址空间的相应存储器页相关联。 每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示，在该约定下，相关联的页面的指令数据将由处理器管线执行。 存储器单元和/或处理器流水线将来自第一页面的执行流程（其相关联的指示符元素指示第一架构或执行约定）识别到第二页面，其第二页面的相关联的指示符元素指示第一个架构或执行约定。 响应于识别，处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。

公开(公告)号：US07941647B2

公开(公告)日：2011-05-10

申请号：US11982419

申请日：2007-10-31

申请人： John S. Yates, Jr. ,  David L. Reese ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Paul H. Hohensee

发明人： John S. Yates, Jr. ,  David L. Reese ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Paul H. Hohensee

IPC分类号： G06F9/22

CPC分类号： G06F9/30189 ,  G06F9/30174 ,  G06F9/30196 ,  G06F9/3802

摘要： A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.

摘要翻译： 一台电脑。 处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。 存储器存储由处理器流水线执行的指令，存储器被划分为页面以供虚拟存储器管理器管理，存储器的单个地址空间具有第一和第二页面。 存储器单元从存储器中取出指令以由流水线执行，并且获取存储的指示符元素，其与要获取指令的单个地址空间的相应存储器页相关联。 每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示，在该约定下，相关联的页面的指令数据将由处理器管线执行。 存储器单元和/或处理器流水线将来自第一页面的执行流程（其相关联的指示符元素指示第一架构或执行约定）识别到第二页面，其第二页面的相关联的指示符元素指示第一个架构或执行约定。 响应于识别，处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。