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17 条记录 (耗时 0.015 秒)

    Polymer de-imprint circuit using negative voltage
    2.
    发明申请
    Polymer de-imprint circuit using negative voltage 有权
    聚合物压印电路使用负电压

    公开(公告)号：US20060087875A1

    公开(公告)日：2006-04-27

    申请号：US10973580

    申请日：2004-10-25

    申请人： Jonathan Lueker ,  Richard Coulson

    发明人： Jonathan Lueker ,  Richard Coulson

    IPC分类号： G11C11/22

    CPC分类号： G11C29/021 ,  G11C11/22 ,  G11C29/02 ,  G11C29/028

    摘要： Briefly, voltages to write a memory cell are adjusted if the memory cell is determined to be imprinted. In one embodiment, a positive voltage not including zero is applied to one of a bit line and a word line and a negative voltage not including zero is applied to another of the bit line and the word line to write a specified logic state to an imprinted memory cell. Neighboring cells do not receive disturb voltages in excess of a disturb voltage threshold.

    摘要翻译： 简而言之，如果确定存储单元被打印，则调整写入存储器单元的电压。 在一个实施例中，将不包括零的正电压施加到位线和字线中的一个，并且不包括零的负电压被施加到位线和字线中的另一个以将指定的逻辑状态写入到印刷 记忆单元 相邻单元不会接收超过干扰电压阈值的干扰电压。

    Temperature adaptive ferro-electric memory access parameters
    4.
    发明申请
    Temperature adaptive ferro-electric memory access parameters 有权
    温度自适应铁电存储器访问参数

    公开(公告)号：US20050288902A1

    公开(公告)日：2005-12-29

    申请号：US10877914

    申请日：2004-06-25

    申请人： Richard Coulson ,  Jonathan Lueker

    发明人： Richard Coulson ,  Jonathan Lueker

    IPC分类号： G06F11/30

    CPC分类号： G11C11/22

    摘要： Briefly, one or more memory access parameters used to access a memory cell are adjusted based on a sensed operating temperature. In one embodiment, a pulse width of an access voltage is increased as the operating temperature decreases below a threshold. In another embodiment, a drive voltage is decreased as the operating temperature increases.

    摘要翻译： 简而言之，基于感测到的工作温度来调整用于访问存储器单元的一个或多个存储器访问参数。 在一个实施例中，当操作温度降低到阈值以下时，存取电压的脉冲宽度增加。 在另一实施例中，驱动电压随着工作温度的升高而降低。

    Digital pulse generator
    5.
    发明授权
    Digital pulse generator 失效
    数字脉冲发生器

    公开(公告)号：US5249132A

    公开(公告)日：1993-09-28

    申请号：US848637

    申请日：1992-03-09

    申请人： Jonathan Lueker ,  John Hengeveld ,  Brad Needham ,  Burt Price ,  Jim Schlegel ,  Mehrab Sedeh

    发明人： Jonathan Lueker ,  John Hengeveld ,  Brad Needham ,  Burt Price ,  Jim Schlegel ,  Mehrab Sedeh

    IPC分类号： H03L7/14 ,  H03L7/189

    CPC分类号： H03L7/189 ,  H03L7/14

    摘要： A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included. This architecture provides controllable tolerances, permits accurate positioning of a trigger out signal relative to any pulse produced, allows the user to specify the trailing edge timing directly, and permits both pulse width and phase to be specified as a percentage of the overall period and automatically kept proportional when the frequency is varied. It also allows synchronized operation of different channels at rates related by powers-of-two, and permits the disabling of a channel at an operator determined voltage level. A means for determining, by the use of an external signal, when bursts of pulses synchronized to an external frequency source will begin, is also provided.

    摘要翻译： 用于脉冲发生器的数字架构包括具有两个可选的频率控制电压源的内部DAC或与外部时基的相位频率比较的可触发压控振荡器（VCO）。 在操作的最高倍频程中，可触发的VCO的输出用于产生输出脉冲，其边缘位置然后通过小的数字增量或“条子”和非常小的模拟增量或“游标”进行调整。 在较低的八度操作中，模式RAM的内容用于将可触发的VCO输出频率分频为2的幂。 RAM内容被转换成串行比特流，其将粗略的脉冲宽度和周期作为整数倍的最高八度周期或量子。 然后边缘位置用条子和游标调整，如顶部八度。 包括自动校准设备。 该架构提供了可控制的公差，允许相对于所产生的任何脉冲的触发输出信号的精确定位，允许用户直接指定后沿时序，并且允许将脉冲宽度和相位指定为整个周期的百分比并且自动地 当频率变化时保持比例。 它还允许以两倍的功率相关的速率同步操作不同的信道，并且允许在操作者确定的电压电平处禁用信道。 还提供了通过使用外部信号来确定何时开始与外部频率源同步的脉冲串的装置。

    Dynamic line balancing scheme for providing inter-packet squelch
    6.
    发明授权
    Dynamic line balancing scheme for providing inter-packet squelch 有权
    用于提供分组间静噪的动态线路平衡方案

    公开(公告)号：US06731687B1

    公开(公告)日：2004-05-04

    申请号：US09422890

    申请日：1999-10-22

    申请人： Jonathan Lueker

    发明人： Jonathan Lueker

    IPC分类号： H04L2502

    CPC分类号： H04L25/0274 ,  H04B3/30 ,  H04L25/10

    摘要： A method for dynamically balancing a serial data link is disclosed. The serial data link includes a first transmission line and a second transmission line. The method includes the steps of creating a DC offset voltage between the first and second transmission lines when the serial data link is in an idle state. When the serial data link is in use to carry data, the DC offset voltage between the first and second transmission lines is removed.

    摘要翻译： 公开了一种用于动态平衡串行数据链路的方法。 串行数据链路包括第一传输线和第二传输线。 该方法包括以下步骤：当串行数据链路处于空闲状态时，在第一和第二传输线之间产生DC偏移电压。 当串行数据链路用于携带数据时，第一和第二传输线之间的直流偏移电压被去除。

    Digital pulse generator using digital slivers and analog vernier increments
    7.
    发明授权
    Digital pulse generator using digital slivers and analog vernier increments 失效
    数字脉冲发生器采用数字式线条和模拟游标增量

    公开(公告)号：US5252977A

    公开(公告)日：1993-10-12

    申请号：US848609

    申请日：1992-03-09

    申请人： Jonathan Lueker ,  John Hengeveld ,  Brad Needham ,  Burt Price ,  Jim Schlegel ,  Mehrab Sedeh

    发明人： Jonathan Lueker ,  John Hengeveld ,  Brad Needham ,  Burt Price ,  Jim Schlegel ,  Mehrab Sedeh

    IPC分类号： H03L7/14 ,  H03L7/189 ,  H03K5/04 ,  H03K5/13

    CPC分类号： H03L7/14 ,  H03L7/189

    摘要： A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included. This architecture provides controllable tolerances, permits accurate positioning of a trigger out signal relative to any pulse produced, allows the user to specify the trailing edge timing directly, and permits both pulse width and phase to be specified as a percentage of the overall period and automatically kept proportional when the frequency is varied. It allows synchronized operation of different channels at rates related by powers-of-two, and permits disabling of a channel at an operator determined voltage level. A means for determining, by the use of an external signal, when bursts of pulses synchronized to an external frequency source will begin, is also provided.

    摘要翻译： 用于脉冲发生器的数字架构包括具有两个可选的频率控制电压源的内部DAC或与外部时基的相位频率比较的可触发压控振荡器（VCO）。 在操作的最高倍频程中，可触发的VCO的输出用于产生输出脉冲，其边缘位置然后通过小的数字增量或“条子”和非常小的模拟增量或“游标”进行调整。 在较低的八度操作中，模式RAM的内容用于将可触发的VCO输出频率分频为2的幂。 RAM内容被转换成串行比特流，其将粗略的脉冲宽度和周期作为整数倍的最高八度周期或量子。 然后边缘位置用条子和游标调整，如顶部八度。 包括自动校准设备。 该架构提供了可控制的公差，允许相对于所产生的任何脉冲的触发输出信号的精确定位，允许用户直接指定后沿时序，并且允许将脉冲宽度和相位指定为整个周期的百分比并且自动地 当频率变化时保持比例。 它允许以两个功率相关的速率同步操作不同的通道，并允许在操作者确定的电压电平下禁用通道。 还提供了通过使用外部信号来确定何时开始与外部频率源同步的脉冲串的装置。

    Minimization of signal loss due to self-erase of imprinted data
    8.
    发明申请
    Minimization of signal loss due to self-erase of imprinted data 有权

    公开(公告)号：US20070002665A1

    公开(公告)日：2007-01-04

    申请号：US11171663

    申请日：2005-06-29

    申请人： Hitesh Windlass ,  Jonathan Lueker

    发明人： Hitesh Windlass ,  Jonathan Lueker

    IPC分类号： G11C5/14

    CPC分类号： G11C11/22

    摘要： The effects of a self-erase phenomenon when accessing imprinted ferroelectric memory cells that have non-conductive electrode interfaces that reduce remnant polarization and decrease signal margin are eliminated. A self-erase control pulse asserted after an access pulse is utilized. The self-erase control pulse has a magnitude sufficient to offset a remnant charge on the non-conductive electrode interfaces after the removal of the access pulse.

    Concurrent asynchronous USB data stream destuffer with variable width bit-wise memory controller
    9.
    发明申请
    Concurrent asynchronous USB data stream destuffer with variable width bit-wise memory controller 审中-公开

    公开(公告)号：US20060075168A1

    公开(公告)日：2006-04-06

    申请号：US11109497

    申请日：2005-04-19

    申请人： Dean Warren ,  Jonathan Lueker

    发明人： Dean Warren ,  Jonathan Lueker

    IPC分类号： G06F13/38

    CPC分类号： G06F13/1678 ,  G06F2213/0042 ,  H03M5/14

    摘要： A concurrent asynchronous USB 2.0 data stream destuffer and separator with variable-width bit-wise memory controller is described. A parallel stream bit destuffer module identifies in parallel one or more stuffed bits in a decoded data field of a received data stream using a six-bit sliding window. The stuffed bits are bits that were inserted into the received USB data stream by a transmitter to force data transitions in the received USB data stream. A data separator module separates the one or more stuffed bits from a plurality of valid data bits in the decoded data field. A memory module generates an incremental pointer value representative of the number of valid bits and writes the plurality of valid data bits from the decoded data field into a variable sized bit-wise memory structure.

    Method of synchronizing signals of a pulse generator
    10.
    发明授权
    Method of synchronizing signals of a pulse generator 失效
    脉冲发生器信号同步的方法

    公开(公告)号：US5224129A

    公开(公告)日：1993-06-29

    申请号：US848638

    申请日：1992-03-09

    申请人： Jonathan Lueker ,  John Hengeveld ,  Brad Needham ,  Burt Price ,  Jim Schlegel ,  Mehrab Sedeh

    发明人： Jonathan Lueker ,  John Hengeveld ,  Brad Needham ,  Burt Price ,  Jim Schlegel ,  Mehrab Sedeh

    IPC分类号： H03L7/14 ,  H03L7/189

    CPC分类号： H03L7/189 ,  H03L7/14

    摘要： A digital architecture for a pulse generator provides a method of synchronizing signals of the pulse generator. The pulse generator has a timebase card, a microprocessor and a plurality of pulse cards. The microprocessor controls the parameters of the timebase card and pulse cards, and the timebase card provides a common master clock signal to all of the pulse cards determined by a triggerable voltage controlled oscillator that has two sources of frequency control voltage, an internal DAC for absolute frequency and a frequency comparison circuit for synchronization with an external timebase. The pulse cards produce pulses, either singly or in bursts, with the leading and trailing edges being separately positionable using quantum, sliver and vernier controls. A pattern RAM on each pulse card provides a pulse pattern that provides an approximation of the desired pulses to one quantum, and repeated iterations through the pattern RAM provide bursts of pulses. Pattern RAMs on different pulse cards, where one pattern is related to the other by a power of two, may be synchronized since both channels use the same master clock from the timebase card. Likewise a burst of pulses may be synchronized with the external timebase since the master clock is synchronized with the external timebase, with a frame sync input signal being used to determine the relative phase between the burst of pulses and the external timebase.

    摘要翻译： 用于脉冲发生器的数字架构提供了一种使脉冲发生器的信号同步的方法。 脉冲发生器具有时基卡，微处理器和多个脉冲卡。 微处理器控制时基卡和脉冲卡的参数，时基卡为所有由具有两个频率控制电压源的可触发压控振荡器确定的所有脉冲卡提供一个共同的主时钟信号，一个绝对的内部DAC 频率和用于与外部时基同步的频率比较电路。 脉冲卡单独或以突发形式产生脉冲，其前导和后沿可使用量子，条子和游标控制单独定位。 每个脉冲卡上的图形RAM提供脉冲图案，其将期望脉冲的近似提供给一个量子，并且通过图案RAM的重复迭代提供脉冲串。 不同脉冲卡上的模式RAM可以同步，因为两个通道使用与时基卡相同的主时钟，其中一个模式与另一个模式相关联。 类似地，脉冲串可以与外部时基同步，因为主时钟与外部时基同步，帧同步输入信号用于确定脉冲串与外部时基之间的相对相位。