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19 条记录 (耗时 0.012 秒)

    Guard ring of a combination wafer or singulated die
    2.
    发明授权
    Guard ring of a combination wafer or singulated die 失效
    组合晶圆或单片模具的保护环

    公开(公告)号：US06879019B2

    公开(公告)日：2005-04-12

    申请号：US10603629

    申请日：2003-06-24

    申请人： Hitesh Windlass ,  Wayne K Ford

    发明人： Hitesh Windlass ,  Wayne K Ford

    IPC分类号： H01L23/00 ,  H01L23/58 ,  H01L29/00

    CPC分类号： H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A combination wafer is manufactured by (i) forming a plurality of alternating dielectric and metal layers, (ii) forming a guard ring trench in the layers, (iii) forming a guard ring layer in the guard ring trench, and then repeating (i), (ii) with a slightly wider guard ring trench, and (iii). A number of layers are thus simultaneously etched and lined with a guard ring layer, but the number of layers is not so large so as to cause lithographic problems that may occur when a deep, narrow guard ring trench is formed. An upper one of the layers that are patterned is always made of silicon dioxide, which includes less carbon than lower polymer layers and allows for a carbon mask to be formed and be easily removed. The slightly wider guard ring trench each time the process is repeated overcomes lithographic alignment problems that may occur when the guard ring trenches are exactly the same size. Subsequent guard ring layers are partially formed on one another, and provide a moisture seal. The guard ring layers are formed at the same time when vias are formed that are connected to electronic elements.

    摘要翻译： 通过（i）形成多个交替的电介质和金属层，（ii）在层中形成保护环沟槽，（iii）在保护环沟槽中形成保护环层，然后重复（i ），（ii）具有略宽的保护环沟槽，和（iii）。 因此，多个层被同时蚀刻并衬有保护环层，但是层的数量不是很大，以致于当形成深而窄的保护环沟槽时可能发生的光刻问题。 图案化的层中的上一层总是由二氧化硅制成，二氧化硅包括比较低聚合物层少的碳，并允许形成碳掩模并容易地除去。 每次重复该过程时，略宽的保护环沟槽克服了当保护环沟槽的尺寸完全相同时可能发生的光刻对准问题。 后续的保护环层彼此部分地形成，并提供湿气密封。 在形成连接到电子元件的通孔的同时形成保护环层。

    Minimization of signal loss due to self-erase of imprinted data
    4.
    发明授权
    Minimization of signal loss due to self-erase of imprinted data 有权
    由于打印数据的自擦除导致的信号丢失最小化

    公开(公告)号：US07283382B2

    公开(公告)日：2007-10-16

    申请号：US11171663

    申请日：2005-06-29

    申请人： Hitesh Windlass ,  Jonathan Lueker

    发明人： Hitesh Windlass ,  Jonathan Lueker

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22

    摘要： The effects of a self-erase phenomenon when accessing imprinted ferroelectric memory cells that have non-conductive electrode interfaces that reduce remnant polarization and decrease signal margin are eliminated. A self-erase control pulse asserted after an access pulse is utilized. The self-erase control pulse has a magnitude sufficient to offset a remnant charge on the non-conductive electrode interfaces after the removal of the access pulse.

    摘要翻译： 消除了具有非导电电极界面的降低剩余极化和降低信号余量的印制铁电存储单元时的自擦除现象的影响。 使用访问脉冲后自动擦除控制脉冲。 自擦除控制脉冲具有足以在去除接入脉冲之后抵消非导电电极接口上的剩余电荷的量值。

    Ferroelectric polymer memory with a thick interface layer
    7.
    发明授权
    Ferroelectric polymer memory with a thick interface layer 有权
    铁电聚合物存储器，具有较厚的界面层

    公开(公告)号：US07170122B2

    公开(公告)日：2007-01-30

    申请号：US10676795

    申请日：2003-09-30

    申请人： Mark R. Richards ,  Daniel C. Diana ,  Hitesh Windlass ,  Wayne K. Ford ,  Ebrahim Andideh

    发明人： Mark R. Richards ,  Daniel C. Diana ,  Hitesh Windlass ,  Wayne K. Ford ,  Ebrahim Andideh

    IPC分类号： H01L27/10

    CPC分类号： G11C13/00 ,  B82Y10/00

    摘要： According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.

    摘要翻译： 根据本发明的一个方面，提供了存储器阵列和构造存储器阵列的方法。 绝缘层形成在半导体衬底上。 然后在绝缘层上形成第一金属叠层。 第一金属叠层被蚀刻以形成第一金属线。 在第一金属线和绝缘层之上形成聚合物层。 聚合物层具有多个粗糙结构的表面。 在聚合物层上形成第二金属叠层，其界面层比粗糙结构层的高度厚。 然后蚀刻第二金属叠层以形成第二金属线。 存储单元形成在第二金属线在第一金属线上延伸的地方。

    Ferroelectric polymer memory with a thick interface layer
    10.
    发明申请
    Ferroelectric polymer memory with a thick interface layer 有权
    铁电聚合物存储器，具有较厚的界面层

    公开(公告)号：US20050104106A1

    公开(公告)日：2005-05-19

    申请号：US11015841

    申请日：2004-12-17

    申请人： Mark Richards ,  Daniel Diana ,  Hitesh Windlass ,  Wayne Ford ,  Ebrahim Andideh

    发明人： Mark Richards ,  Daniel Diana ,  Hitesh Windlass ,  Wayne Ford ,  Ebrahim Andideh

    IPC分类号： G03C5/00 ,  G11C13/00 ,  H01L21/00 ,  H01L21/336 ,  H01L29/94 ,  H01L31/113

    CPC分类号： G11C13/00 ,  B82Y10/00

    摘要： According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.

    摘要翻译： 根据本发明的一个方面，提供了存储器阵列和构造存储器阵列的方法。 绝缘层形成在半导体衬底上。 然后在绝缘层上形成第一金属叠层。 第一金属叠层被蚀刻以形成第一金属线。 在第一金属线和绝缘层之上形成聚合物层。 聚合物层具有多个粗糙结构的表面。 在聚合物层上形成第二金属叠层，其界面层比粗糙结构层的高度厚。 然后蚀刻第二金属叠层以形成第二金属线。 存储单元形成在第二金属线在第一金属线上延伸的地方。