公开(公告)号：US20080133864A1

公开(公告)日：2008-06-05

申请号：US11566149

申请日：2006-12-01

Applicant: Jonathan Randall Hinkle ,  Aaron Mitchell Richardson ,  Ganesh Balakrishnan

Inventor： Jonathan Randall Hinkle ,  Aaron Mitchell Richardson ,  Ganesh Balakrishnan

IPC: G06F12/06

CPC classification number: G06F12/0811 ,  G06F12/0804

Abstract: An apparatus, system, and method are disclosed for caching fully buffered memory (FBM) data. A circuit card is connected to an FBM socket that is configured to receive a FBM. An interface module communicates with a memory controller and at least one FBM via the FBM socket through a plurality of electrical interfaces. A cache controller apportions memory space in the cache memory between each FBM of the at least one FBM according to an apportionment policy. A cache memory transparently stores data from the at least one FBM and the memory controller and transparently provides the data to the memory controller. The cache controller manages coherency between the at least one FBM and the cache memory.

Abstract translation: 公开了用于缓存全缓冲存储器（FBM）数据的装置，系统和方法。 电路卡连接到配置为接收FBM的FBM插座。 接口模块通过多个电接口经由FBM插座与存储器控制器和至少一个FBM通信。 缓存控制器根据分配策略来分配至少一个FBM的每个FBM之间的高速缓冲存储器中的存储器空间。 缓存存储器透明地存储来自至少一个FBM和存储器控制器的数据，并将数据透明地提供给存储器控制器。 高速缓存控制器管理至少一个FBM和高速缓冲存储器之间的一致性。

公开(公告)号：US20100030942A1

公开(公告)日：2010-02-04

申请号：US12184430

申请日：2008-08-01

Applicant: Jonathan Randall Hinkle ,  Justin Potok Bandholz

Inventor： Jonathan Randall Hinkle ,  Justin Potok Bandholz

IPC: G06F12/06

CPC classification number: G06F12/06 ,  G06F12/0607

Abstract: Method and systems are disclosed for increasing the number of ranks supported in a memory system. In one embodiment, a plurality of predefined subsets of memory chips on a memory module is selected. A chip select signal uniquely identifying the selected subset of memory chips is generated. The chip select signal is encoded as a multi-bit word having a bit width that is less than the number of predefined subsets of memory chips. Each bit of the encoded chip select signal is transmitted along a separate chip select line. The transmitted chip select signal is decoded to determine the identity of the selected subset of memory chips. The selected subset of memory chips identified by the decoded chip select signal are read or written.

Abstract translation: 公开了用于增加在存储器系统中支持的等级数量的方法和系统。 在一个实施例中，选择存储器模块上的多个预定义的存储器芯片子集。 产生唯一地识别所选择的存储器芯片子集的芯片选择信号。 芯片选择信号被编码为具有小于存储器芯片的预定义子集的数目的位宽度的多位字。 编码芯片选择信号的每一位沿独立的芯片选择线传输。 所传送的芯片选择信号被解码以确定所选择的存储芯片子集的身份。 由解码的芯片选择信号识别的所选存储器芯片的子集被读取或写入。

公开(公告)号：US09104557B2

公开(公告)日：2015-08-11

申请号：US12184430

申请日：2008-08-01

Applicant: Jonathan Randall Hinkle ,  Justin Potok Bandholz

Inventor： Jonathan Randall Hinkle ,  Justin Potok Bandholz

IPC: G06F12/06

CPC classification number: G06F12/06 ,  G06F12/0607

Abstract: Method and systems are disclosed for increasing the number of ranks supported in a memory system. In one embodiment, a plurality of predefined subsets of memory chips on a memory module is selected. A chip select signal uniquely identifying the selected subset of memory chips is generated. The chip select signal is encoded as a multi-bit word having a bit width that is less than the number of predefined subsets of memory chips. Each bit of the encoded chip select signal is transmitted along a separate chip select line. The transmitted chip select signal is decoded to determine the identity of the selected subset of memory chips. The selected subset of memory chips identified by the decoded chip select signal are read or written.

Abstract translation: 公开了用于增加在存储器系统中支持的等级数量的方法和系统。 在一个实施例中，选择存储器模块上的多个预定义的存储器芯片子集。 产生唯一地识别所选择的存储器芯片子集的芯片选择信号。 芯片选择信号被编码为具有小于存储器芯片的预定义子集的数目的位宽度的多位字。 编码芯片选择信号的每一位沿独立的芯片选择线传输。 所传送的芯片选择信号被解码以确定所选择的存储器芯片子集的身份。 由解码的芯片选择信号识别的所选存储器芯片的子集被读取或写入。

公开(公告)号：US08000105B2

公开(公告)日：2011-08-16

申请号：US12172580

申请日：2008-07-14

Applicant: Jonathan Randall Hinkle

Inventor： Jonathan Randall Hinkle

IPC: H05K1/00

CPC classification number: G06F1/20 ,  H05K1/117 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/047 ,  H05K2201/056 ,  H05K2201/09745 ,  H05K2201/10159 ,  H05K2203/302 ,  Y10T29/49002

Abstract: Memory systems and methods of forming memory modules. In one embodiment, a computer memory system includes a substantially tubular frame with an elongate card edge extending along the frame. A flexible circuit comprising a flexible substrate, a plurality of memory chips affixed to the flexible substrate, and a plurality of electrical terminals interconnected with the memory chips, is secured along a perimeter of the tubular frame with the electrical terminals arranged along the card edge.

Abstract translation: 内存系统和形成内存模块的方法。 在一个实施例中，计算机存储器系统包括具有沿框架延伸的细长卡边缘的基本上管状的框架。 包括柔性基板，固定到柔性基板的多个存储芯片以及与存储芯片互连的多个电端子的柔性电路沿着管状框架的周边被固定，电端子沿卡边缘布置。

公开(公告)号：US20090088008A1

公开(公告)日：2009-04-02

申请号：US11865819

申请日：2007-10-02

Applicant: Justin Potok Bandholz ,  Jonathan Randall Hinkle ,  Clifton Ehrich Kerr ,  John Frank Nations, Jr. ,  William James Sommerville

Inventor： Justin Potok Bandholz ,  Jonathan Randall Hinkle ,  Clifton Ehrich Kerr ,  John Frank Nations, Jr. ,  William James Sommerville

IPC: H01R12/16 ,  H01R13/62

CPC classification number: H01R12/85 ,  H01R12/7076 ,  H05K7/1007

Abstract: Method and apparatus for installing a processor into electronic communication with a socket. The land grid array socket connector includes a socket housing secured to a circuit board and an array of upwardly extending pins for electronic communication with contact pads on the processor. The socket connector provides a carriage configured to receiving the processor through a lateral opening and support a perimeter edge of the processor. A mechanical linkage couples the carriage and the socket housing for substantially vertically translating the processor relative to the socket. A plurality of alignment features upwardly extends from the socket housing along the perimeter of the array of pins. Each of the alignment features has an inwardly-facing tapered surface for registering the edge of the processor and biasing the processor into a position where the array of contact pads are aligned with the array of pins as the processor is lowered.

Abstract translation: 用于将处理器安装到与插座进行电子通信的方法和装置。 地面阵列插座连接器包括固定到电路板的插座壳体和用于与处理器上的接触垫电子通信的向上延伸的针阵列。 插座连接器提供了一个托架，其构造成通过侧开口接收处理器并且支撑处理器的周边边缘。 机械联动装置联接滑架和插座壳体，以使处理器相对于插座基本垂直地平移。 多个对准特征从插座壳体沿引脚阵列的周边向上延伸。 每个对准特征具有向内的锥形表面，用于对准处理器的边缘并且将处理器偏置为处理器降低时接触焊盘阵列与引脚阵列对准的位置。

公开(公告)号：US07507102B1

公开(公告)日：2009-03-24

申请号：US11865819

申请日：2007-10-02

Applicant: Justin Potok Bandholz ,  Jonathan Randall Hinkle ,  Clifton Ehrich Kerr ,  John Frank Nations, Jr. ,  William James Sommerville

Inventor： Justin Potok Bandholz ,  Jonathan Randall Hinkle ,  Clifton Ehrich Kerr ,  John Frank Nations, Jr. ,  William James Sommerville

IPC: H01R4/50

CPC classification number: H01R12/85 ,  H01R12/7076 ,  H05K7/1007

Abstract: Method and apparatus for installing a processor into electronic communication with a socket. The land grid array socket connector includes a socket housing secured to a circuit board and an array of upwardly extending pins for electronic communication with contact pads on the processor. The socket connector provides a carriage configured to receiving the processor through a lateral opening and support a perimeter edge of the processor. A mechanical linkage couples the carriage and the socket housing for substantially vertically translating the processor relative to the socket. A plurality of alignment features upwardly extends from the socket housing along the perimeter of the array of pins. Each of the alignment features has an inwardly-facing tapered surface for registering the edge of the processor and biasing the processor into a position where the array of contact pads are aligned with the array of pins as the processor is lowered.

Abstract translation: 用于将处理器安装到与插座进行电子通信的方法和装置。 地面阵列插座连接器包括固定到电路板的插座壳体和用于与处理器上的接触垫电子通信的向上延伸的针阵列。 插座连接器提供了一个托架，其构造成通过侧开口接收处理器并且支撑处理器的周边边缘。 机械联动装置联接滑架和插座壳体，以使处理器相对于插座基本垂直地平移。 多个对准特征从插座壳体沿引脚阵列的周边向上延伸。 每个对准特征具有向内的锥形表面，用于对准处理器的边缘并且将处理器偏置为处理器降低时接触焊盘阵列与引脚阵列对准的位置。