Method and apparatus for converting interface between high speed data having various capacities
    1.
    发明授权
    Method and apparatus for converting interface between high speed data having various capacities 有权
    用于转换具有各种容量的高速数据之间的接口的方法和装置

    公开(公告)号:US07624311B2

    公开(公告)日:2009-11-24

    申请号:US11947349

    申请日:2007-11-29

    IPC分类号: G06K5/04

    CPC分类号: H04J3/1611 H04L25/14

    摘要: Provided are a method and an apparatus for converting an interface between high speed data having various capacities. The apparatus includes a data transmitting part and a data receiving part. The data transmitting part generates a deskew channel having respective timing data of a plurality of data transmitted from a first communicating device, and outputs the generated deskew channel together with the plurality of data to a second communicating device. The data receiving part compares the deskew channel transmitted from the second communicating device with the plurality of data to measure skew values of the data, aligns bits and bytes of the plurality of data using the skew values, and transmits the plurality of data to the first communicating device.

    摘要翻译: 提供了一种用于转换具有各种容量的高速数据之间的接口的方法和装置。 该装置包括数据发送部分和数据接收部分。 数据发送部生成具有从第一通信装置发送的多个数据的各自的定时数据的歪斜通道,并将生成的歪斜通道与多个数据一起输出到第二通信装置。 数据接收部将从第二通信装置发送的歪斜通道与多个数据进行比较,以测量数据的偏斜值,使用偏斜值对准多个数据的比特和字节,并将多个数据发送到第一个 通讯设备

    Apparatus and method for receiving parallel SFI-5 data interfaced with very high-speed deserializer
    2.
    发明申请
    Apparatus and method for receiving parallel SFI-5 data interfaced with very high-speed deserializer 有权
    用于接收与非常高速解串器接口的并行SFI-5数据的装置和方法

    公开(公告)号:US20090150708A1

    公开(公告)日:2009-06-11

    申请号:US12316280

    申请日:2008-12-11

    IPC分类号: G06F11/00 H04L29/04

    CPC分类号: H04L25/14 H03M9/00

    摘要: The development of transmission technologies have resulted in a several tens Gbps optical transmission system. In the present invention, a low-speed FPGA receives a plurality of several Gbps signals according to a very high-speed parallel converting unit and the SFI-5, divides each of the plurality of several Gbps signals into a plurality of several hundreds (Mbps) parallel signals, and processes the plurality of several hundreds (Mbps) parallel signals in order to constitute an SFI-5 receiving end.

    摘要翻译: 传输技术的发展已经导致了数十Gbps光传输系统。 在本发明中,低速FPGA根据非常高速的并行转换单元接收多个Gbps信号,并且SFI-5将多个Gbps信号中的每一个分成多个数百(Mbps) )并行信号,并且处理多个数百个(Mbps)并行信号,以构成SFI-5接收端。

    OPERATION CIRCUIT FOR MODIFIED EUCLIDEAN ALGORITHM IN HIGH-SPEED REED-SOLOMON DECODER AND METHOD OF IMPLEMENTING THE MODIFIED EUCLIDEAN ALGORITHM
    3.
    发明申请
    OPERATION CIRCUIT FOR MODIFIED EUCLIDEAN ALGORITHM IN HIGH-SPEED REED-SOLOMON DECODER AND METHOD OF IMPLEMENTING THE MODIFIED EUCLIDEAN ALGORITHM 审中-公开
    用于高速解码器解码器的改进的EUCLIDEAN算法的操作电路和实现改进的EUCLIDEAN算法的方法

    公开(公告)号:US20080313253A1

    公开(公告)日:2008-12-18

    申请号:US12051503

    申请日:2008-03-19

    IPC分类号: G06F11/08

    CPC分类号: H03M13/1535 H03M13/6575

    摘要: Provided are an operation circuit for a modified Euclidean algorithm in a high-speed Reed-Solomon (RS) decoder and a method of implementing the modified Euclidean algorithm. Since a finite state machine (FSM) for generating a stop signal and an FSM for generating a control signal that controls a swap operation, a shift operation, and a polynomial operation for each basic cell of the modified Euclidean algorithm are used, an area-efficient RS decoder can be realized without using a conventional degree computation unit for comparing and calculating degrees.

    摘要翻译: 提供了一种用于高速里德 - 所罗门(RS)解码器中的修改的欧几里德算法的操作电路和实现修改的欧几里德算法的方法。 由于使用用于产生停止信号的有限状态机(FSM)和用于产生控制交换操作的控制信号的FSM,所以使用修改的欧几里德算法的每个基本单元的移位操作和多项式操作, 可以在不使用用于比较和计算度的常规度计算单元的情况下实现高效的RS解码器。

    Method and apparatus for verifying multi-channel data
    4.
    发明授权
    Method and apparatus for verifying multi-channel data 有权
    用于验证多通道数据的方法和装置

    公开(公告)号:US07500156B2

    公开(公告)日:2009-03-03

    申请号:US11417980

    申请日:2006-05-04

    IPC分类号: G11B20/20 G11B20/14

    CPC分类号: H04L1/242

    摘要: A multi-channel data verifying apparatus and method are provided. The apparatus includes a receiver receiving N data channels and a deskew channel generated by sequentially extracting a predetermined data bit from the each of N data channels, and a deskew channel error detector detecting whether the deskew channel received by the receiver corresponds to an expected deskew channel generated and stored based on the test signal or generated based on the previously received deskew channel. Accordingly, data channels, a deskew channel and the entire data capacity can be verified and thus the cause of a problem in the transmission and reception of multi-channel data can be identified in advance.

    摘要翻译: 提供了一种多通道数据验证装置和方法。 该装置包括接收N个数据信道的接收机和通过从N个数据信道中的每一个顺序地提取预定的数据位而生成的去歪斜信道,以及歪斜通道误差检测器,检测由接收机接收的歪斜通道是否对应于预期的歪斜通道 基于测试信号生成和存储,或者基于先前接收到的偏移通道生成。 因此,可以验证数据信道,歪斜通道和整个数据容量,因此可以预先识别多信道数据的发送和接收中的问题的原因。

    APPARATUS FOR AND METHOD OF AUTOMATICALLY CONTROLLING SKEW BETWEEN TRANSMITTED DATA
    7.
    发明申请
    APPARATUS FOR AND METHOD OF AUTOMATICALLY CONTROLLING SKEW BETWEEN TRANSMITTED DATA 审中-公开
    自动控制传输数据之间的距离的装置和方法

    公开(公告)号:US20090129455A1

    公开(公告)日:2009-05-21

    申请号:US12184505

    申请日:2008-08-01

    IPC分类号: H04B17/00

    摘要: Provided is an apparatus for and method of automatically controlling skew between transmitted data, which is caused when a common low-speed field-programmable gate array (FPGA) transmits signals having a transmission rate in the range of tens of Gbps to an optical transponder. The apparatus and method can transmit data with a transmission rate of several Gbps irrespective of the type of the FPGA.

    摘要翻译: 提供了一种自动控制发送数据之间的偏移的装置和方法,这是在公共低速现场可编程门阵列(FPGA)将具有在数十Gbps范围内的传输速率的信号发送到光学应答器时引起的。 该装置和方法可以以几Gbps的传输速率发送数据,而不管FPGA的类型。

    APPARATUS FOR TRANSMITTING AND RECEIVING DATA WITH VARIOUS DATA CAPACITIES AT HIGH SPEED
    8.
    发明申请
    APPARATUS FOR TRANSMITTING AND RECEIVING DATA WITH VARIOUS DATA CAPACITIES AT HIGH SPEED 审中-公开
    用于以高速传输和接收各种数据容量的数据的装置

    公开(公告)号:US20090046745A1

    公开(公告)日:2009-02-19

    申请号:US12120132

    申请日:2008-05-13

    IPC分类号: H04L29/02 H04J3/04

    CPC分类号: H04J3/047

    摘要: There is provided an apparatus for transmitting and receiving data with various data capacity at high speed. The apparatus for transmitting and receiving data includes a client signal interface block converting client signals being received through media into a high-capacity electrical signal and selectively interfacing the converted high-capacity electrical signal through high-speed multi-channel; a framer receiving the selectively interfaced electrical signal from the client signal interface block and multiplexing and mapping the received electrical signal into 40 G multi-channel frame signals; and a SERDES & transceiver receiving the 40 G multi-channel frame signals from the framer, multiplexing the received multi-channel frame signals with the 40 G serial signals and transmitting the multiplexed 40 G serial signals. The apparatus for transmitting and receiving data may be useful to decrease its space and stably receive client signals by selectively interfacing various client signals with replacing the client signal interface blocks only, depending on the client signals to be supplied to the same transmitting/receiving apparatus.

    摘要翻译: 提供了一种用于以高速度发送和接收具有各种数据容量的数据的装置。 用于发送和接收数据的装置包括客户端信号接口块,其将通过媒体接收的客户端信号转换为高容量电信号,并通过高速多通道选择性地接合经转换的高容量电信号; 成帧器从客户端信号接口块接收有选择地接口的电信号,并将所接收的电信号复用并映射成40G多信道帧信号; 以及从成帧器接收40G多信道帧信号的SERDES&收发器,用40G串行信号复用接收的多信道帧信号,并发送多路复用的40G串行信号。 用于发送和接收数据的装置可以通过根据要提供给同一发送/接收装置的客户端信号选择性地将各种客户信号替换为客户信号接口块来选择性地接口来减小其空间并稳定地接收客户端信号是有用的。

    Apparatus and method for transmitting and receiving data
    9.
    发明授权
    Apparatus and method for transmitting and receiving data 有权
    用于发送和接收数据的装置和方法

    公开(公告)号:US08473820B2

    公开(公告)日:2013-06-25

    申请号:US12781953

    申请日:2010-05-18

    IPC分类号: H03M13/00 H03M13/03

    摘要: A transmitting apparatus in a transport network, which performs forward error correcting encoding for each virtual lane set, which is a multiple of the number of transmission channels, in order to generate virtual frames including independent parity bytes for each of the virtual lanes. These generated virtual frames are transmitted through at least one transmission channel. A receiving apparatus for detecting the virtual frames for each virtual lane from a signal received through a transmission channel by using a frame assignment sequence, and performing forward error correcting decoding by using the parity bytes included in the virtual frames detected for each virtual lane.

    摘要翻译: 传输网络中的发送装置,其为每个虚拟通道组执行前向纠错编码,每个虚拟通道组是传输通道数量的倍数,以便生成包括每个虚拟通道的独立奇偶校验字节的虚拟帧。 这些生成的虚拟帧通过至少一个传输信道传输。 一种用于通过使用帧分配序列从通过传输信道接收的信号中检测每个虚拟通道的虚拟帧的接收装置,并且通过使用包括在针对每个虚拟通道检测的虚拟帧中的奇偶校验字节来执行前向纠错解码。

    Apparatus and method for receiving parallel SFI-5 data interfaced with very high-speed deserializer
    10.
    发明授权
    Apparatus and method for receiving parallel SFI-5 data interfaced with very high-speed deserializer 有权
    用于接收与非常高速解串器接口的并行SFI-5数据的装置和方法

    公开(公告)号:US08127172B2

    公开(公告)日:2012-02-28

    申请号:US12316280

    申请日:2008-12-11

    IPC分类号: G06F1/04

    CPC分类号: H04L25/14 H03M9/00

    摘要: The development of transmission technologies have resulted in a several tens Gbps optical transmission system. In the present invention, a low-speed FPGA receives a plurality of several Gbps signals according to a very high-speed parallel converting unit and the SFI-5, divides each of the plurality of several Gbps signals into a plurality of several hundreds (Mbps) parallel signals, and processes the plurality of several hundreds (Mbps) parallel signals in order to constitute an SFI-5 receiving end.

    摘要翻译: 传输技术的发展已经导致了数十Gbps光传输系统。 在本发明中,低速FPGA根据非常高速的并行转换单元接收多个Gbps信号,并且SFI-5将多个Gbps信号中的每一个分成多个数百(Mbps) )并行信号,并且处理多个数百个(Mbps)并行信号,以构成SFI-5接收端。