公开(公告)号：US06404011B2

公开(公告)日：2002-06-11

申请号：US09865004

申请日：2001-05-23

Applicant: Jong-Dae Kim ,  Sang-Gi Kim ,  Jin-Gun Koo ,  Dae-Yong Kim

Inventor： Jong-Dae Kim ,  Sang-Gi Kim ,  Jin-Gun Koo ,  Dae-Yong Kim

IPC: H01L2976

CPC classification number: H01L21/84 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1203

Abstract: A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.

Abstract translation: 一种制造半导体功率集成电路的方法包括以下步骤：形成具有至少一个有源区的半导体结构，其中有源区包括用于形成源的阱区和用于形成漏极区的漂移区，形成用于 有源区的隔离，其中沟槽具有来自半导体结构的表面的预定深度，在沟槽内部和半导体结构之上形成第一TEOS氧化物层，其中第一TEOS氧化物层具有来自该半导体结构的预定厚度 在所述第一TEOS氧化物层上形成第二TEOS氧化物层，其中所述第二TEOS氧化物层的厚度小于所述第一TEOS氧化物层的厚度，并且对所述第一TEOS氧化物层进行选择性蚀刻 第一和第二TEOS氧化物层，从而同时形成场氧化物层图案，二极管绝缘层图案和栅极氧化物层图案 y减少加工步骤并获得低导通电阻。

公开(公告)号：US06284605B1

公开(公告)日：2001-09-04

申请号：US09428403

申请日：1999-10-28

Applicant: Jong-Dae Kim ,  Sang-Gi Kim ,  Jin-Gun Koo ,  Dae-Yong Kim

Inventor： Jong-Dae Kim ,  Sang-Gi Kim ,  Jin-Gun Koo ,  Dae-Yong Kim

IPC: H01L21336

CPC classification number: H01L21/84 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1203

Abstract: A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.

Abstract translation: 一种制造半导体功率集成电路的方法包括以下步骤：形成具有至少一个有源区的半导体结构，其中有源区包括用于形成源的阱区和用于形成漏极区的漂移区，形成用于 有源区的隔离，其中沟槽具有来自半导体结构的表面的预定深度，在沟槽内部和半导体结构之上形成第一TEOS氧化物层，其中第一TEOS氧化物层具有来自该半导体结构的预定厚度 在所述第一TEOS氧化物层上形成第二TEOS氧化物层，其中所述第二TEOS氧化物层的厚度小于所述第一TEOS氧化物层的厚度，并且对所述第一TEOS氧化物层进行选择性蚀刻 第一和第二TEOS氧化物层，从而同时形成场氧化物层图案，二极管绝缘层图案和栅极氧化物层图案 y减少加工步骤并获得低导通电阻。

公开(公告)号：US06337659B1

公开(公告)日：2002-01-08

申请号：US09426198

申请日：1999-10-25

Applicant: Sang-Gi Kim

Inventor： Sang-Gi Kim

IPC: H01Q326

CPC classification number: H04B7/0805 ,  H01Q1/246 ,  H01Q3/30 ,  H01Q25/008 ,  H04B7/10 ,  Y02D70/122 ,  Y02D70/442 ,  Y02D70/444

Abstract: A phased array antenna system having low power amplifiers reduces power loss through several tens meters high frequency cables. The antenna system for transmitting a signal in a base station, comprising: a phased array unit for selecting an input signal through one of a plurality of beam ports, for dividing the input signal into a plurality of signals and for outputting the plurality of signals through a plurality of array ports, each of the signal having a linear phase difference according to difference of propagation path; a switch for receiving the input signal from a base station, for selecting one of the plurality of beam ports of said phased array and for transmitting the input signal to the selected beam port, responsive to a control signal transmitted from the base station; a plurality of low power amplifiers for low power amplifying the plurality of signals inputted from the plurality of array ports of said phased array; and phased array antennas for radiating the plurality of signals from said plurality of low power amplifiers, thereby providing a spatial power summation into a direction of equiphase plane allowing effective radiated power sufficiently enough to cover a cell into a steered direction selected by said switch.

Abstract translation: 具有低功率放大器的相控阵天线系统通过数十米高频电缆降低功率损耗。 用于在基站中发送信号的天线系统，包括：相控阵单元，用于通过多个波束端口之一选择输入信号，用于将输入信号分成多个信号，并通过 多个阵列端口，每个信号根据传播路径的差异具有线性相位差; 用于从基站接收输入信号的开关，用于选择所述相控阵列的多个波束端口中的一个并响应于从基站发送的控制信号将输入信号发射到所选波束端口; 多个低功率放大器，用于低功率放大从所述相控阵列的多个阵列端口输入的多个信号; 以及用于从所述多个低功率放大器辐射多个信号的相控阵天线，由此向同相平面的方向提供空间功率求和，从而允许足够有效的辐射功率将小区覆盖成由所述开关选择的转向方向。

公开(公告)号：US20090061378A1

公开(公告)日：2009-03-05

申请号：US12159522

申请日：2006-12-22

Applicant: In-Jae Kim ,  Sang-Gi Kim ,  Seung-Jae Park ,  Ji-Hun Jung ,  Chang-Seob Han ,  Seong-Chul Shin

Inventor： In-Jae Kim ,  Sang-Gi Kim ,  Seung-Jae Park ,  Ji-Hun Jung ,  Chang-Seob Han ,  Seong-Chul Shin

IPC: A61C7/20 ,  B21F43/00

CPC classification number: A61C7/20 ,  A61C2201/007 ,  B22F2999/00 ,  Y10T29/49568 ,  B22F5/12 ,  B22F7/04

Abstract: The present invention relates to an orthodontic wire and a manufacturing method thereof, and more particularly, to an orthodontic wire, which is not harmful to the human body and is capable of continuously holding the color of teeth, and a manufacturing method of the orthodontic wire. According to the present invention, there is provided an orthodontic wire, comprising a metal wire formed of a shape memory alloy material; a silver (Ag) film applied to a surface of the metal wire; and a polymer compound film applied to a surface of the silver (Ag) film to prevent the silver (Ag) film from being discolored.

Abstract translation: 本发明涉及一种正畸线及其制造方法，更具体地，涉及一种对人体无害并能够持续保持牙齿颜色的正畸线，以及正畸线的制造方法 。 根据本发明，提供了一种正畸线，其包括由形状记忆合金材料形成的金属线; 施加到金属线表面的银（Ag）膜; 以及施加到银（Ag）膜的表面上以防止银（Ag）膜变色的高分子化合物膜。