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公开(公告)号：US06404011B2
公开(公告)日：2002-06-11
申请号：US09865004
申请日：2001-05-23
Applicant: Jong-Dae Kim , Sang-Gi Kim , Jin-Gun Koo , Dae-Yong Kim
Inventor： Jong-Dae Kim , Sang-Gi Kim , Jin-Gun Koo , Dae-Yong Kim
IPC: H01L2976
CPC classification number: H01L21/84 , H01L21/76264 , H01L21/76283 , H01L27/1203
Abstract: A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.
Abstract translation: 一种制造半导体功率集成电路的方法包括以下步骤：形成具有至少一个有源区的半导体结构，其中有源区包括用于形成源的阱区和用于形成漏极区的漂移区，形成用于 有源区的隔离，其中沟槽具有来自半导体结构的表面的预定深度，在沟槽内部和半导体结构之上形成第一TEOS氧化物层，其中第一TEOS氧化物层具有来自该半导体结构的预定厚度 在所述第一TEOS氧化物层上形成第二TEOS氧化物层，其中所述第二TEOS氧化物层的厚度小于所述第一TEOS氧化物层的厚度，并且对所述第一TEOS氧化物层进行选择性蚀刻 第一和第二TEOS氧化物层，从而同时形成场氧化物层图案，二极管绝缘层图案和栅极氧化物层图案 y减少加工步骤并获得低导通电阻。
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公开(公告)号：US06284605B1
公开(公告)日：2001-09-04
申请号：US09428403
申请日：1999-10-28
Applicant: Jong-Dae Kim , Sang-Gi Kim , Jin-Gun Koo , Dae-Yong Kim
Inventor： Jong-Dae Kim , Sang-Gi Kim , Jin-Gun Koo , Dae-Yong Kim
IPC: H01L21336
CPC classification number: H01L21/84 , H01L21/76264 , H01L21/76283 , H01L27/1203
Abstract: A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.
Abstract translation: 一种制造半导体功率集成电路的方法包括以下步骤：形成具有至少一个有源区的半导体结构，其中有源区包括用于形成源的阱区和用于形成漏极区的漂移区，形成用于 有源区的隔离，其中沟槽具有来自半导体结构的表面的预定深度，在沟槽内部和半导体结构之上形成第一TEOS氧化物层，其中第一TEOS氧化物层具有来自该半导体结构的预定厚度 在所述第一TEOS氧化物层上形成第二TEOS氧化物层，其中所述第二TEOS氧化物层的厚度小于所述第一TEOS氧化物层的厚度，并且对所述第一TEOS氧化物层进行选择性蚀刻 第一和第二TEOS氧化物层，从而同时形成场氧化物层图案，二极管绝缘层图案和栅极氧化物层图案 y减少加工步骤并获得低导通电阻。
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公开(公告)号：US20120098057A1
公开(公告)日：2012-04-26
申请号：US13228479
申请日：2011-09-09
Applicant: Sang Gi KIM , Jin-Gun Koo , Seong Wook Yoo , Jong-Moon Park , Jin Ho Lee , Kyoung Il Na , Yil Suk Yang , Jongdae Kim
Inventor： Sang Gi KIM , Jin-Gun Koo , Seong Wook Yoo , Jong-Moon Park , Jin Ho Lee , Kyoung Il Na , Yil Suk Yang , Jongdae Kim
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7813 , H01L21/2255 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/66727 , H01L29/66734 , H01L29/7811
Abstract: Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer.
Abstract translation: 提供半导体器件及其制造方法。 该方法包括：在第一导电类型的半导体衬底中形成沟槽; 在所述沟槽的侧壁和底表面上形成包含第二导电类型的掺杂剂的沟槽掺杂剂层; 通过将所述沟槽掺杂剂含量层中的掺杂剂扩散到所述半导体衬底中来形成掺杂区域; 并去除含沟槽掺杂剂层。
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公开(公告)号：US08629020B2
公开(公告)日：2014-01-14
申请号：US13228479
申请日：2011-09-09
Applicant: Sang Gi Kim , Jin-Gun Koo , Seong Wook Yoo , Jong-Moon Park , Jin Ho Lee , Kyoung Il Na , Yil Suk Yang , Jongdae Kim
Inventor： Sang Gi Kim , Jin-Gun Koo , Seong Wook Yoo , Jong-Moon Park , Jin Ho Lee , Kyoung Il Na , Yil Suk Yang , Jongdae Kim
IPC: H01L21/336
CPC classification number: H01L29/7813 , H01L21/2255 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/66727 , H01L29/66734 , H01L29/7811
Abstract: Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer.
Abstract translation: 提供半导体器件及其制造方法。 该方法包括：在第一导电类型的半导体衬底中形成沟槽; 在所述沟槽的侧壁和底表面上形成包含第二导电类型的掺杂剂的沟槽掺杂剂层; 通过将所述沟槽掺杂剂含量层中的掺杂剂扩散到所述半导体衬底中来形成掺杂区域; 并去除含沟槽掺杂剂层。
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