公开(公告)号：US06404011B2

公开(公告)日：2002-06-11

申请号：US09865004

申请日：2001-05-23

Applicant: Jong-Dae Kim ,  Sang-Gi Kim ,  Jin-Gun Koo ,  Dae-Yong Kim

Inventor： Jong-Dae Kim ,  Sang-Gi Kim ,  Jin-Gun Koo ,  Dae-Yong Kim

IPC: H01L2976

CPC classification number: H01L21/84 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1203

Abstract: A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.

Abstract translation: 一种制造半导体功率集成电路的方法包括以下步骤：形成具有至少一个有源区的半导体结构，其中有源区包括用于形成源的阱区和用于形成漏极区的漂移区，形成用于 有源区的隔离，其中沟槽具有来自半导体结构的表面的预定深度，在沟槽内部和半导体结构之上形成第一TEOS氧化物层，其中第一TEOS氧化物层具有来自该半导体结构的预定厚度 在所述第一TEOS氧化物层上形成第二TEOS氧化物层，其中所述第二TEOS氧化物层的厚度小于所述第一TEOS氧化物层的厚度，并且对所述第一TEOS氧化物层进行选择性蚀刻 第一和第二TEOS氧化物层，从而同时形成场氧化物层图案，二极管绝缘层图案和栅极氧化物层图案 y减少加工步骤并获得低导通电阻。

公开(公告)号：US06284605B1

公开(公告)日：2001-09-04

申请号：US09428403

申请日：1999-10-28

Applicant: Jong-Dae Kim ,  Sang-Gi Kim ,  Jin-Gun Koo ,  Dae-Yong Kim

Inventor： Jong-Dae Kim ,  Sang-Gi Kim ,  Jin-Gun Koo ,  Dae-Yong Kim

IPC: H01L21336

CPC classification number: H01L21/84 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1203

Abstract: A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.

Abstract translation: 一种制造半导体功率集成电路的方法包括以下步骤：形成具有至少一个有源区的半导体结构，其中有源区包括用于形成源的阱区和用于形成漏极区的漂移区，形成用于 有源区的隔离，其中沟槽具有来自半导体结构的表面的预定深度，在沟槽内部和半导体结构之上形成第一TEOS氧化物层，其中第一TEOS氧化物层具有来自该半导体结构的预定厚度 在所述第一TEOS氧化物层上形成第二TEOS氧化物层，其中所述第二TEOS氧化物层的厚度小于所述第一TEOS氧化物层的厚度，并且对所述第一TEOS氧化物层进行选择性蚀刻 第一和第二TEOS氧化物层，从而同时形成场氧化物层图案，二极管绝缘层图案和栅极氧化物层图案 y减少加工步骤并获得低导通电阻。

公开(公告)号：US09235992B2

公开(公告)日：2016-01-12

申请号：US13493225

申请日：2012-06-11

Applicant: Seung-Jin Yang ,  Dae-Yong Kim ,  Nam-Hyuk Kim ,  Seung-Hun Jeong ,  Byeong-Jin Kim ,  In-Bae Chang

Inventor： Seung-Jin Yang ,  Dae-Yong Kim ,  Nam-Hyuk Kim ,  Seung-Hun Jeong ,  Byeong-Jin Kim ,  In-Bae Chang

IPC: G09B23/28

CPC classification number: G09B23/288

Abstract: There is provided a simulator for CPR and defibrillator training, which may perform training and evaluation of CPR and a defibrillator so that when there is a patient in an emergency situation, effective first aid can be provided to the patient. Through the simulator for CPR and defibrillator training, CPR and the use of the defibrillator for emergency medical technicians such as a doctor, a nurse and an emergency medical technician can be systematically and repetitively trained, and a person in charge of training can identify whether or not the education is performed effectively by recording and evaluating a training situation. Also, through the simulator, the education of CPR and defibrillator training is possible so that not only the emergency medical technicians but also general people can perform emergency treatment effectively.

Abstract translation: 提供了用于CPR和除颤器训练的模拟器，其可以执行CPR和除颤器的训练和评估，使得当患者处于紧急情况时，可以向患者提供有效的急救。 通过CPR和除颤器训练的模拟器，可以系统地和重复地训练CPR和使用医生，护士和紧急医疗技术人员等紧急医疗技术人员的除颤器，负责训练的人员可以识别是否 不是通过记录和评估培训情况来有效地进行教育。 此外，通过模拟器，CPR和除颤器培训的教育是可能的，不仅紧急医疗技术人员和普通人员可以有效地进行紧急处理。

公开(公告)号：US20130330698A1

公开(公告)日：2013-12-12

申请号：US13493225

申请日：2012-06-11

Applicant: Seung-Jin YANG ,  Dae-Yong Kim ,  Nam-Hyuk Kim ,  Seung-Hun Jeong ,  Byeong-Jin Kim ,  In-Bae Chang

Inventor： Seung-Jin YANG ,  Dae-Yong Kim ,  Nam-Hyuk Kim ,  Seung-Hun Jeong ,  Byeong-Jin Kim ,  In-Bae Chang

IPC: G09B23/32

CPC classification number: G09B23/288

Abstract: There is provided a simulator for CPR and defibrillator training, which may perform training and evaluation of CPR and a defibrillator so that when there is a patient in an emergency situation, effective first aid can be provided to the patient. Through the simulator for CPR and defibrillator training, CPR and the use of the defibrillator for emergency medical technicians such as a doctor, a nurse and an emergency medical technician can be systematically and repetitively trained, and a person in charge of training can identify whether or not the education is performed effectively by recording and evaluating a training situation. Also, through the simulator, the education of CPR and defibrillator training is possible so that not only the emergency medical technicians but also general people can perform emergency treatment effectively.

Abstract translation: 提供了用于CPR和除颤器训练的模拟器，其可以执行CPR和除颤器的训练和评估，使得当患者处于紧急情况时，可以向患者提供有效的急救。 通过CPR和除颤器训练的模拟器，可以系统地和重复地训练CPR和使用医生，护士和紧急医疗技术人员等紧急医疗技术人员的除颤器，负责训练的人员可以识别是否 不是通过记录和评估培训情况来有效地进行教育。 此外，通过模拟器，CPR和除颤器培训的教育是可能的，不仅紧急医疗技术人员和普通人员可以有效地进行紧急处理。

公开(公告)号：US07867898B2

公开(公告)日：2011-01-11

申请号：US11772953

申请日：2007-07-03

Applicant: Dae-Yong Kim ,  Jong-Ho Yun ,  Hyun-Su Kim ,  Eun-Ji Jung ,  Eun-Ok Lee

Inventor： Dae-Yong Kim ,  Jong-Ho Yun ,  Hyun-Su Kim ,  Eun-Ji Jung ,  Eun-Ok Lee

IPC: H01L21/44

CPC classification number: H01L21/28518 ,  H01L21/76843 ,  H01L21/76855

Abstract: A method of forming an ohmic contact layer including forming an insulation layer pattern on a substrate, the insulation pattern layer having an opening selectively exposing a silicon bearing layer, forming a metal layer on the exposed silicon bearing layer using an electrode-less plating process, and forming a metal silicide layer from the silicon bearing layer and the metal layer using a silicidation process. Also, a method of forming metal wiring in a semiconductor device using the foregoing method of forming an ohmic contact layer.

Abstract translation: 一种形成欧姆接触层的方法，包括在基板上形成绝缘层图案，所述绝缘图案层具有选择性地暴露含硅层的开口，使用无电极电镀工艺在暴露的硅轴承层上形成金属层， 以及使用硅化法从所述硅轴承层和所述金属层形成金属硅化物层。 另外，使用上述形成欧姆接触层的方法在半导体器件中形成金属布线的方法。

公开(公告)号：US07846796B2

公开(公告)日：2010-12-07

申请号：US12791692

申请日：2010-06-01

Applicant: Jong-Ho Yun ,  Byung-Hee Kim ,  Dae-Yong Kim ,  Hyun-Su Kim ,  Eun-Ji Jung ,  Eun-Ok Lee

Inventor： Jong-Ho Yun ,  Byung-Hee Kim ,  Dae-Yong Kim ,  Hyun-Su Kim ,  Eun-Ji Jung ,  Eun-Ok Lee

IPC: H01L21/336 ,  H01L21/425 ,  H01L21/44

CPC classification number: H01L27/10885 ,  H01L27/10876

Abstract: A semiconductor device includes a plurality of channel structures on a semiconductor substrate. A bit line groove having opposing sidewalls is defined between sidewalls of adjacent ones of the plurality of channel structures. A plurality of bit lines are formed on corresponding ones of the opposing sidewalls, and the plurality of bit lines are electrically isolated from each other

Abstract translation: 半导体器件包括半导体衬底上的多个沟道结构。 具有相对侧壁的位线槽限定在多个通道结构中的相邻侧壁之间。 多个位线形成在对置的相对的侧壁的相应的一个上，多个位线彼此电隔离

公开(公告)号：US07733695B2

公开(公告)日：2010-06-08

申请号：US11653866

申请日：2007-01-17

Applicant: Dae-Yong Kim ,  Sang-Won Hwang ,  Jun-Yong Park

Inventor： Dae-Yong Kim ,  Sang-Won Hwang ,  Jun-Yong Park

IPC: G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.

Abstract translation: 在一个实施例中，非易失性存储器件包括形成在衬底中的第一导电类型的阱以及与阱中形成的位线串联连接的第一多个存储单元晶体管。 在阱外部的衬底中形成缓冲器，并连接到位线。 至少一个去耦合晶体管被配置为从位线去耦合缓冲器，并且在阱中形成去耦合晶体管。

公开(公告)号：US06274920B1

公开(公告)日：2001-08-14

申请号：US09448729

申请日：1999-11-24

Applicant: Min Park ,  Hyun-Kyu Yu ,  Cheon-Soo Kim ,  Chung-Hwan Kim ,  Dae-Yong Kim

Inventor： Min Park ,  Hyun-Kyu Yu ,  Cheon-Soo Kim ,  Chung-Hwan Kim ,  Dae-Yong Kim

IPC: H01L2900

CPC classification number: H01L28/10 ,  H01L27/08

Abstract: A method for fabricating an inductor device includes the steps of forming a plurality of trenches in a substrate by selectively etching the substrate, implanting dopants into sidewalls and bottom portion of each trench, forming an oxide layer by oxidizing the trenches and the substrate and simultaneously forming a doped layer in the surroundings of the trenches by diffusing the dopants into the substrate, and forming a dielectric layer on a resultant structure to fill the entrance of the trenches, thereby forming air-gap layers inside the trenches, thereby reducing a parasitic capacitance and a magnetic coupling.

Abstract translation: 一种用于制造电感器件的方法包括以下步骤：通过选择性蚀刻衬底在衬底中形成多个沟槽，将掺杂剂注入每个沟槽的侧壁和底部，通过氧化沟槽和衬底形成氧化物层并同时形成 通过将掺杂剂扩散到衬底中并在所得结构上形成介电层以填充沟槽的入口，从而在沟槽内形成气隙层，从而减小寄生电容，并且 磁耦合。

公开(公告)号：US11202441B2

公开(公告)日：2021-12-21

申请号：US16649459

申请日：2018-09-21

Applicant: Dae-Yong Kim

Inventor： Dae-Yong Kim ,  Seung-Hee Son

IPC: A01K15/02 ,  F21V33/00

Abstract: A pet exercise apparatus includes: a base module; a running module which has an exercise space formed therein in an axial direction and an inner circumferential surface or outer circumferential surface rotatably coupled to the base module; and an LED module provided in the base module or the running module to irradiate LED light to the exercise space. The pet exercise system may further includes: a rotary module which has an exercise space part formed therein as a space in which the pet may exercise and a gaze inducing part provided on an inner circumferential surface and inducing a pet's gaze so that the pet continuously moves in the exercise space part and may exercise; a support module supporting the rotary module so that the rotary module is rotatable according to the motion of the pet; a control module controlling an operation of the gaze inducing part; and a terminal including a communication part transmitting an operation control signal CI of the gaze inducing part to be transmitted to the control module.

公开(公告)号：US10043902B2

公开(公告)日：2018-08-07

申请号：US14963731

申请日：2015-12-09

Applicant: Chung-Hwan Shin ,  Sang-Bom Kang ,  Dae-Yong Kim ,  Jeong-Ik Kim ,  Chul-Sung Kim ,  Je-Hyung Ryu ,  Sang-Woo Lee ,  Hyo-Seok Choi

Inventor： Chung-Hwan Shin ,  Sang-Bom Kang ,  Dae-Yong Kim ,  Jeong-Ik Kim ,  Chul-Sung Kim ,  Je-Hyung Ryu ,  Sang-Woo Lee ,  Hyo-Seok Choi

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/40 ,  H01L21/285 ,  H01L21/265 ,  H01L29/165 ,  H01L23/485 ,  H01L21/768 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L29/7839 ,  H01L21/26506 ,  H01L21/28 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/76814 ,  H01L23/485 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/401 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/78 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.