Conductive coating composition for protective film and method for producing coating layer using the same
    1.
    发明授权
    Conductive coating composition for protective film and method for producing coating layer using the same 失效
    保护膜用导电性涂料组合物及其制造方法

    公开(公告)号:US07393474B2

    公开(公告)日:2008-07-01

    申请号:US11715349

    申请日:2007-03-08

    IPC分类号: H01B1/00

    CPC分类号: H01B1/124

    摘要: A conductive coating composition and a method for producing coating layer using the same are disclosed. The conductive coating composition is capable of forming an antistatic coating layer on the protective film surface of display device. The conductive coating composition includes: 1 to 30 wt % of polyethylene dioxythiophene aqueous-dispersed solution; 5 to 15 wt % of water-soluble binder resin; 0.2 to 10 wt % of melamine resin; 6 to 40 wt % of alcohol solvent; 5 to 30 wt % of organic solvent selected from the group consisting of dimethyl sulfoxide, propyleneglycol methylether, N-methylpyrrolidone, ethyl-3-ethoxypropionate, propyleneglycol monomethyletheracetate, butylcarbitol and the mixtures thereof; and 10 to 50 wt % of water. The method for producing the conductive coating layer includes the steps of coating the conductive coating composition on a substrate; and drying the coating composition.

    摘要翻译: 公开了一种导电涂料组合物及其制备方法。 导电性涂料组合物能够在显示装置的保护膜表面上形成抗静电涂层。 导电性涂料组合物包括:1〜30重量%的聚乙烯二氧噻吩水分散溶液; 5〜15重量%的水溶性粘合剂树脂; 0.2〜10重量%的三聚氰胺树脂; 6〜40重量%的醇溶剂; 5〜30重量%的选自二甲基亚砜,丙二醇甲基醚,N-甲基吡咯烷酮,3-乙氧基丙酸乙酯,丙二醇单甲醚基乙酸酯,丁基卡必醇及其混合物的有机溶剂; 和10〜50重量%的水。 导电性涂层的制造方法包括将导电性涂料组合物涂布在基材上的工序; 并干燥涂料组合物。

    Conductive coating composition for protective film and method for producing coating layer using the same
    2.
    发明申请
    Conductive coating composition for protective film and method for producing coating layer using the same 失效
    保护膜用导电性涂料组合物及其制造方法

    公开(公告)号:US20070257235A1

    公开(公告)日:2007-11-08

    申请号:US11715349

    申请日:2007-03-08

    IPC分类号: H01B1/12

    CPC分类号: H01B1/124

    摘要: A conductive coating composition and a method for producing coating layer using the same are disclosed. The conductive coating composition is capable of forming an antistatic coating layer on the protective film surface of display device. The conductive coating composition includes: 1 to 30 wt % of polyethylene dioxythiophene aqueous-dispersed solution; 5 to 15 wt % of water-soluble binder resin; 0.2 to 10 wt % of melamine resin; 6 to 40 wt % of alcohol solvent; 5 to 30 wt % of organic solvent selected from the group consisting of dimethyl sulfoxide, propyleneglycol methylether, N-methylpyrrolidone, ethyl-3-ethoxypropionate, propyleneglycol monomethyletheracetate, butylcarbitol and the mixtures thereof; and 10 to 50 wt % of water. The method for producing the conductive coating layer includes the steps of coating the conductive coating composition on a substrate; and drying the coating composition.

    摘要翻译: 公开了一种导电涂料组合物及其制备方法。 导电性涂料组合物能够在显示装置的保护膜表面上形成抗静电涂层。 导电性涂料组合物包括:1〜30重量%的聚乙烯二氧噻吩水分散溶液; 5〜15重量%的水溶性粘合剂树脂; 0.2〜10重量%的三聚氰胺树脂; 6〜40重量%的醇溶剂; 5〜30重量%的选自二甲基亚砜,丙二醇甲基醚,N-甲基吡咯烷酮,3-乙氧基丙酸乙酯,丙二醇单甲醚基乙酸酯,丁基卡必醇及其混合物的有机溶剂; 和10〜50重量%的水。 导电性涂层的制造方法包括将导电性涂料组合物涂布在基材上的工序; 并干燥涂料组合物。

    Sliding/folding combination type portable digital communication apparatus and hinge unit thereof
    3.
    发明申请
    Sliding/folding combination type portable digital communication apparatus and hinge unit thereof 审中-公开
    滑动/折叠组合型便携式数字通信设备及其铰链单元

    公开(公告)号:US20060135227A1

    公开(公告)日:2006-06-22

    申请号:US11261892

    申请日:2005-10-28

    IPC分类号: H04M1/00

    摘要: Disclosed herein is a sliding/folding combination type portable digital communication apparatus that includes a body; a sliding folder having a first position in which it is constrained on the body, a second position in which it has slid a predetermined distance while continuously facing the body, and a third position in which it has rotated away from the body after the sliding in such a manner that it does not face the body; and a sliding hinge module positioned between the body and the sliding folder to travel together with the sliding folder and provide a force necessary for folding/unfolding the sliding folder. The user can conveniently use a single communication apparatus having the advantages of both sliding-type and folding-type apparatuses.

    摘要翻译: 本文公开了一种滑动/折叠组合型便携式数字通信装置,其包括主体; 具有第一位置的滑动夹具,其被限制在所述主体上;第二位置,其在所述第二位置中在连续面向所述主体的同时已经滑动预定距离;以及第三位置,在所述第三位置中,所述第二位置在滑动之后已经远离所述身体旋转 这样一种不会面对身体的方式; 以及定位在主体和滑动夹具之间的滑动铰链模块,以与滑动夹具一起移动并提供折叠/展开滑动夹具所需的力。 用户可以方便地使用具有滑动型和折叠型装置两者的优点的单个通信装置。

    Data delay control circuit and method
    5.
    发明授权
    Data delay control circuit and method 失效
    数据延迟控制电路及方法

    公开(公告)号:US08305127B2

    公开(公告)日:2012-11-06

    申请号:US12726565

    申请日:2010-03-18

    申请人: Jong-Chul Shin

    发明人: Jong-Chul Shin

    IPC分类号: H03H11/26

    摘要: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal. Consequently, the data delay circuit can automatically generate a data delay signal according to the changes in the operating environment.

    摘要翻译: 一种数据延迟控制电路和方法,其可以自适应地反映诸如工作温度,工作电压和半导体芯片的制造过程的操作环境的变化。 数据延迟控制电路设计成能够在设计半导体芯片时需要预定时间段的预期延迟时适应地延迟数据。 数据延迟电路包括可以反映延迟单元的延迟周期的变化并且自动调整延迟单元的延迟周期的时钟振荡单元。 由于数据延迟电路包括监视电路和多个延迟路径,所以数据延迟电路可以提供具有所需延迟值的延迟路径。 因此,即使当半导体器件的工作环境改变时,数据延迟电路也可以控制数据信号的延迟周期。 因此,数据延迟电路可以根据操作环境的变化自动生成数据延迟信号。

    DATA DELAY CONTROL CIRCUIT AND METHOD
    6.
    发明申请
    DATA DELAY CONTROL CIRCUIT AND METHOD 失效
    数据延迟控制电路及方法

    公开(公告)号:US20100182064A1

    公开(公告)日:2010-07-22

    申请号:US12726565

    申请日:2010-03-18

    申请人: Jong-Chul Shin

    发明人: Jong-Chul Shin

    IPC分类号: H03H11/26

    摘要: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal. Consequently, the data delay circuit can automatically generate a data delay signal according to the changes in the operating environment.

    摘要翻译: 一种数据延迟控制电路和方法,其可以自适应地反映诸如工作温度,工作电压和半导体芯片的制造过程的操作环境的变化。 数据延迟控制电路设计成能够在设计半导体芯片时需要预定时间段的预期延迟时适应地延迟数据。 数据延迟电路包括可以反映延迟单元的延迟周期的变化并且自动调整延迟单元的延迟周期的时钟振荡单元。 由于数据延迟电路包括监视电路和多个延迟路径,所以数据延迟电路可以提供具有所需延迟值的延迟路径。 因此,即使当半导体器件的工作环境改变时,数据延迟电路也可以控制数据信号的延迟周期。 因此,数据延迟电路可以根据操作环境的变化自动生成数据延迟信号。

    Data delay control circuit and method
    7.
    发明授权
    Data delay control circuit and method 失效
    数据延迟控制电路及方法

    公开(公告)号:US07696802B2

    公开(公告)日:2010-04-13

    申请号:US11669296

    申请日:2007-01-31

    申请人: Jong-Chul Shin

    发明人: Jong-Chul Shin

    IPC分类号: H03H11/26

    摘要: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal. Consequently, the data delay circuit can automatically generate a data delay signal according to the changes in the operating environment.

    摘要翻译: 一种数据延迟控制电路和方法,其可以自适应地反映诸如工作温度,工作电压和半导体芯片的制造过程的操作环境的变化。 数据延迟控制电路设计成能够在设计半导体芯片时需要预定时间段的预期延迟时适应地延迟数据。 数据延迟电路包括可以反映延迟单元的延迟周期的变化并且自动调整延迟单元的延迟周期的时钟振荡单元。 由于数据延迟电路包括监视电路和多个延迟路径,所以数据延迟电路可以提供具有所需延迟值的延迟路径。 因此,即使当半导体器件的工作环境改变时,数据延迟电路也可以控制数据信号的延迟周期。 因此,数据延迟电路可以根据操作环境的变化自动生成数据延迟信号。

    System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC
    8.
    发明授权
    System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC 失效
    具有内置自检电路的片上系统(SOC)和SOC的自检方法

    公开(公告)号:US07761763B2

    公开(公告)日:2010-07-20

    申请号:US12182785

    申请日:2008-07-30

    IPC分类号: G01R31/28

    CPC分类号: G01R31/318335

    摘要: A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

    摘要翻译: 提供了具有内置自检(BIST)电路的片上系统(SOC)和SOC的自检方法。 具有BIST电路的SOC包括具有BIST逻辑电路的知识产权(IP)块和BIST控制单元。 BIST逻辑电路响应于通过系统总线接收的控制数据在正常或测试模式下工作,并在测试模式下输出测试结果数据。 BIST控制单元通过系统总线将控制数据,命令信号,测试模式数据和测试地址信号传输到BIST逻辑电路来测试IP模块,并将通过系统总线接收的测试结果数据进行压缩和存储 测试模式。

    SYSTEM-ON-CHIP (SOC) HAVING BUILT-IN-SELF-TEST CIRCUITS AND A SELF-TEST METHOD OF THE SOC
    9.
    发明申请
    SYSTEM-ON-CHIP (SOC) HAVING BUILT-IN-SELF-TEST CIRCUITS AND A SELF-TEST METHOD OF THE SOC 失效
    具有内置自检电路的系统芯片(SOC)和SOC的自检方法

    公开(公告)号:US20080313515A1

    公开(公告)日:2008-12-18

    申请号:US12182785

    申请日:2008-07-30

    IPC分类号: G01R31/3187 G06F11/27

    CPC分类号: G01R31/318335

    摘要: A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

    摘要翻译: 提供了具有内置自检(BIST)电路的片上系统(SOC)和SOC的自检方法。 具有BIST电路的SOC包括具有BIST逻辑电路的知识产权(IP)块和BIST控制单元。 BIST逻辑电路响应于通过系统总线接收的控制数据在正常或测试模式下工作,并在测试模式下输出测试结果数据。 BIST控制单元通过系统总线将控制数据,命令信号,测试模式数据和测试地址信号传输到BIST逻辑电路来测试IP模块,并将通过系统总线接收的测试结果数据进行压缩和存储 测试模式。

    System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC
    10.
    发明授权
    System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC 有权
    具有内置自检电路的片上系统(SOC)和SOC的自检方法

    公开(公告)号:US07421635B2

    公开(公告)日:2008-09-02

    申请号:US11066585

    申请日:2005-02-25

    IPC分类号: G01R31/28

    CPC分类号: G01R31/318335

    摘要: A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

    摘要翻译: 提供了具有内置自检(BIST)电路的片上系统(SOC)和SOC的自检方法。 具有BIST电路的SOC包括具有BIST逻辑电路的知识产权(IP)块和BIST控制单元。 BIST逻辑电路响应于通过系统总线接收的控制数据在正常或测试模式下工作,并在测试模式下输出测试结果数据。 BIST控制单元通过系统总线将控制数据,命令信号,测试模式数据和测试地址信号传输到BIST逻辑电路来测试IP模块,并将通过系统总线接收的测试结果数据进行压缩和存储 测试模式。