公开(公告)号：US08890881B2

公开(公告)日：2014-11-18

申请号：US11843206

申请日：2007-08-22

申请人： Jong-chul Shin ,  Kee-won Joe ,  Sang-jun Yang

发明人： Jong-chul Shin ,  Kee-won Joe ,  Sang-jun Yang

IPC分类号： G09G5/399 ,  G06F13/00 ,  G06F12/02 ,  H04N7/01 ,  H04N19/426 ,  H04N5/14

CPC分类号： H04N5/14 ,  H04N7/01 ,  H04N19/182 ,  H04N19/426

摘要： Provided are a mapping method and a video system for mapping pixel data included in the same pixel group to the same bank of a memory, A method for mapping the position of pixel data of a picture to an address of a memory comprises a pixel group dividing operation and an address mapping operation. The pixel group dividing operation divides the pixels of the picture into at least one pixel group. The address mapping operation maps pixel data of pixels included in the same pixel group to the same bank of the memory.

摘要翻译： 提供了一种用于将包括在相同像素组中的像素数据映射到存储器的同一组的映射方法和视频系统。用于将图像的像素数据的位置映射到存储器的地址的方法包括：像素组划分 操作和地址映射操作。 像素组分割操作将图像的像素划分为至少一个像素组。 地址映射操作将包括在相同像素组中的像素的像素数据映射到存储器的同一组。

公开(公告)号：US20080126691A1

公开(公告)日：2008-05-29

申请号：US11783516

申请日：2007-04-10

申请人： Sang-jun Yang ,  Jong-chul Shin

发明人： Sang-jun Yang ,  Jong-chul Shin

IPC分类号： G06F12/00

CPC分类号： G06F13/1684 ,  G06F12/0253 ,  G06F13/1642 ,  Y02D10/13 ,  Y02D10/14

摘要： Provided are an apparatus and method for partially accessing a DRAM. The apparatus for partially accessing a DRAM includes a memory controller. The memory controller includes a first sub-controller which controls a first DRAM and a second sub-controller which controls a second DRAM. Accordingly, a garbage cycle, i.e., an operation which wastes data transfer bandwidth, that may generate when a related art DRAM accessing apparatus is used, is removed.

摘要翻译： 提供了用于部分访问DRAM的装置和方法。 用于部分访问DRAM的装置包括存储器控制器。 存储器控制器包括控制第一DRAM的第一子控制器和控制第二DRAM的第二子控制器。 因此，去除了当使用现有的DRAM访问装置时可能产生的垃圾循环，即浪费数据传输带宽的操作。

公开(公告)号：US07761763B2

公开(公告)日：2010-07-20

申请号：US12182785

申请日：2008-07-30

申请人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

发明人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

IPC分类号： G01R31/28

CPC分类号： G01R31/318335

摘要： A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

摘要翻译： 提供了具有内置自检（BIST）电路的片上系统（SOC）和SOC的自检方法。 具有BIST电路的SOC包括具有BIST逻辑电路的知识产权（IP）块和BIST控制单元。 BIST逻辑电路响应于通过系统总线接收的控制数据在正常或测试模式下工作，并在测试模式下输出测试结果数据。 BIST控制单元通过系统总线将控制数据，命令信号，测试模式数据和测试地址信号传输到BIST逻辑电路来测试IP模块，并将通过系统总线接收的测试结果数据进行压缩和存储 测试模式。

公开(公告)号：US07622152B2

公开(公告)日：2009-11-24

申请号：US11482840

申请日：2006-07-10

申请人： Jae Soo Kim ,  Kyeung Ho Kim ,  Ji Young Byun ,  Jin-Kook Yoon ,  Doo Yong Kim ,  Jong Kown Lee ,  Jong Chul Shin ,  Dae Ho Rho

发明人： Jae Soo Kim ,  Kyeung Ho Kim ,  Ji Young Byun ,  Jin-Kook Yoon ,  Doo Yong Kim ,  Jong Kown Lee ,  Jong Chul Shin ,  Dae Ho Rho

IPC分类号： C23C16/00 ,  C23C16/26 ,  B05D1/40 ,  B05D3/02 ,  B05D3/04

CPC分类号： C23C8/02 ,  C23C10/02 ,  C23C12/00 ,  Y10T428/31678

摘要： A MoSi2—Si3N4 composite coating which is coated on a surface of base materials. The MoSi2—Si3N4 composite coating on the surface of the base material can be formed by forming a Mo2N diffusion layer by vapor-depositing of nitrogen on the surface of the base material and forming a MoSi2—Si3N4 composite coating by vapor-depositing of silicon on the surface of the Mo2N diffusion layer, or the MoSi2—Si3N4 composite coating on the surface of the base material can be formed by forming a MoSi2 diffusion layer by vapor-depositing of silicon on a surface of a base material by the CVD method, transforming the MoSi2 diffusion layer into a Mo5Si3 diffusion layer by heating under a high-purity hydrogen or argon atmosphere, forming a MoSi2—Si3N4 composite diffusion layer by vapor-depositing of nitrogen on the surface of the MosSi3 diffusion layer by the CVD method and forming a MoSi2—Si3N4 composite coating by vapor-depositing of silicon on the surface of the MoSi2—Si3N4 composite diffusion layer.

摘要翻译： 涂覆在基材表面的MoSi2-Si3N4复合涂层。 可以通过在基材表面上气相沉积氮形成Mo2N扩散层并通过在硅上气相沉积形成MoSi2-Si3N4复合涂层来形成基体材料表面上的MoSi2-Si3N4复合涂层 Mo2N扩散层的表面或基体材料表面的MoSi2-Si3N4复合涂层可以通过CVD法在基材表面上气相沉积硅形成MoSi 2扩散层而形成， 通过在高纯度氢或氩气氛下加热，将MoSi 2扩散层进入Mo5Si3扩散层，通过CVD法在MosSi 3扩散层的表面上气相沉积形成MoSi 2 -Si 3 N 4复合扩散层，并形成 MoSi2-Si3N4复合涂层，通过在MoSi2-Si3N4复合扩散层的表面上气相沉积硅。

公开(公告)号：US20080313515A1

公开(公告)日：2008-12-18

申请号：US12182785

申请日：2008-07-30

申请人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

发明人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

IPC分类号： G01R31/3187 ,  G06F11/27

CPC分类号： G01R31/318335

摘要： A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

摘要翻译： 提供了具有内置自检（BIST）电路的片上系统（SOC）和SOC的自检方法。 具有BIST电路的SOC包括具有BIST逻辑电路的知识产权（IP）块和BIST控制单元。 BIST逻辑电路响应于通过系统总线接收的控制数据在正常或测试模式下工作，并在测试模式下输出测试结果数据。 BIST控制单元通过系统总线将控制数据，命令信号，测试模式数据和测试地址信号传输到BIST逻辑电路来测试IP模块，并将通过系统总线接收的测试结果数据进行压缩和存储 测试模式。

公开(公告)号：US07421635B2

公开(公告)日：2008-09-02

申请号：US11066585

申请日：2005-02-25

申请人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

发明人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

IPC分类号： G01R31/28

CPC分类号： G01R31/318335

摘要： A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

摘要翻译： 提供了具有内置自检（BIST）电路的片上系统（SOC）和SOC的自检方法。 具有BIST电路的SOC包括具有BIST逻辑电路的知识产权（IP）块和BIST控制单元。 BIST逻辑电路响应于通过系统总线接收的控制数据在正常或测试模式下工作，并在测试模式下输出测试结果数据。 BIST控制单元通过系统总线将控制数据，命令信号，测试模式数据和测试地址信号传输到BIST逻辑电路来测试IP模块，并将通过系统总线接收的测试结果数据进行压缩和存储 测试模式。

公开(公告)号：US07412550B2

公开(公告)日：2008-08-12

申请号：US11035741

申请日：2005-01-18

申请人： Kee-Won Joe ,  Jong-Ho Kim ,  Hae-Young Rha ,  Jong-Chul Shin

发明人： Kee-Won Joe ,  Jong-Ho Kim ,  Hae-Young Rha ,  Jong-Chul Shin

IPC分类号： G06F13/00

CPC分类号： G06F13/364

摘要： A bus system including a bus arbiter and a plurality of masters. The bus arbiter grants bus control to one of the plurality of masters. When a master with bus control sends a read command, bus control is transferred to another one of the plurality of masters, thereby increasing the efficiency of the bus system. A method including sending a read command and transferring bus control to another one of a plurality of masters before receiving the response to the read command.

摘要翻译： 一种总线系统，包括总线仲裁器和多个主机。 总线仲裁器将总线控制权授予多个主机之一。 当具有总线控制的主机发送读取命令时，总线控制被传送到多个主机中的另一个，从而提高总线系统的效率。 一种方法，包括在接收对所述读取命令的响应之前发送读取命令并将总线控制传送到多个主机中的另一个主机。

公开(公告)号：US08227715B2

公开(公告)日：2012-07-24

申请号：US12696288

申请日：2010-01-29

申请人： Jung-Won Park ,  Jong-Chul Shin ,  Jong-Kyun Shin ,  Young-Bae Ji

发明人： Jung-Won Park ,  Jong-Chul Shin ,  Jong-Kyun Shin ,  Young-Bae Ji

IPC分类号： H01H9/26

CPC分类号： H01H13/88 ,  H01H13/83 ,  H01H13/86 ,  H01H2223/04 ,  H01H2229/022 ,  H01H2229/044 ,  H04M1/23

摘要： A keypad assembly mounted in a portable terminal is disclosed. The keypad assembly has a window keypad including a display window disposed on a front face of the portable terminal. A keypad top is integrally molded with the display window and simultaneously assembled on the front face of the portable terminal, thereby providing an easier assembly than known heretofore, as two parts can be assembled at the same time and additionally provide an elegant exterior front face.

摘要翻译： 公开了安装在便携式终端中的小键盘组件。 键盘组件具有包括设置在便携式终端的正面上的显示窗口的窗口键盘。 键盘顶部与显示窗一体地模制，同时组装在便携式终端的前表面上，从而提供了比迄今为止更容易的组装，因为两个部件可以同时组装，并且另外提供优雅的外部正面。

公开(公告)号：US20100200386A1

公开(公告)日：2010-08-12

申请号：US12696288

申请日：2010-01-29

申请人： Jung-Won PARK ,  Jong-Chul SHIN ,  Jong-Kyun SHIN ,  Young-Bae JI

发明人： Jung-Won PARK ,  Jong-Chul SHIN ,  Jong-Kyun SHIN ,  Young-Bae JI

IPC分类号： H01H13/76

CPC分类号： H01H13/88 ,  H01H13/83 ,  H01H13/86 ,  H01H2223/04 ,  H01H2229/022 ,  H01H2229/044 ,  H04M1/23

摘要： A keypad assembly mounted in a portable terminal is disclosed. The keypad assembly has a window keypad including a display window disposed on a front face of the portable terminal. A keypad top is integrally molded with the display window and simultaneously assembled on the front face of the portable terminal, thereby providing an easier assembly than known heretofore, as two parts can be assembled at the same time and additionally provide an elegant exterior front face.

摘要翻译： 公开了安装在便携式终端中的小键盘组件。 键盘组件具有包括设置在便携式终端的正面上的显示窗口的窗口键盘。 键盘顶部与显示窗一体地模制，同时组装在便携式终端的前表面上，从而提供了比迄今为止更容易的组装，因为两个部件可以同时组装，并且另外提供优雅的外部正面。

公开(公告)号：US07393474B2

公开(公告)日：2008-07-01

申请号：US11715349

申请日：2007-03-08

申请人： Jong-Dai Park ,  Jong-Chul Shin ,  Ho-Kyu Lee

发明人： Jong-Dai Park ,  Jong-Chul Shin ,  Ho-Kyu Lee

IPC分类号： H01B1/00

CPC分类号： H01B1/124

摘要： A conductive coating composition and a method for producing coating layer using the same are disclosed. The conductive coating composition is capable of forming an antistatic coating layer on the protective film surface of display device. The conductive coating composition includes: 1 to 30 wt % of polyethylene dioxythiophene aqueous-dispersed solution; 5 to 15 wt % of water-soluble binder resin; 0.2 to 10 wt % of melamine resin; 6 to 40 wt % of alcohol solvent; 5 to 30 wt % of organic solvent selected from the group consisting of dimethyl sulfoxide, propyleneglycol methylether, N-methylpyrrolidone, ethyl-3-ethoxypropionate, propyleneglycol monomethyletheracetate, butylcarbitol and the mixtures thereof; and 10 to 50 wt % of water. The method for producing the conductive coating layer includes the steps of coating the conductive coating composition on a substrate; and drying the coating composition.

摘要翻译： 公开了一种导电涂料组合物及其制备方法。 导电性涂料组合物能够在显示装置的保护膜表面上形成抗静电涂层。 导电性涂料组合物包括：1〜30重量％的聚乙烯二氧噻吩水分散溶液; 5〜15重量％的水溶性粘合剂树脂; 0.2〜10重量％的三聚氰胺树脂; 6〜40重量％的醇溶剂; 5〜30重量％的选自二甲基亚砜，丙二醇甲基醚，N-甲基吡咯烷酮，3-乙氧基丙酸乙酯，丙二醇单甲醚基乙酸酯，丁基卡必醇及其混合物的有机溶剂; 和10〜50重量％的水。 导电性涂层的制造方法包括将导电性涂料组合物涂布在基材上的工序; 并干燥涂料组合物。