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    System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC
    3.
    发明申请
    System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC 有权
    具有内置自检电路的片上系统（SOC）和SOC的自检方法

    公开(公告)号：US20050204233A1

    公开(公告)日：2005-09-15

    申请号：US11066585

    申请日：2005-02-25

    申请人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

    发明人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

    IPC分类号： G01R31/28 ,  G06F11/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

    CPC分类号： G01R31/318335

    摘要： A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

    摘要翻译： 提供了具有内置自检（BIST）电路的片上系统（SOC）和SOC的自检方法。 具有BIST电路的SOC包括具有BIST逻辑电路的知识产权（IP）块和BIST控制单元。 BIST逻辑电路响应于通过系统总线接收的控制数据在正常或测试模式下工作，并在测试模式下输出测试结果数据。 BIST控制单元通过系统总线将控制数据，命令信号，测试模式数据和测试地址信号传输到BIST逻辑电路来测试IP模块，并将通过系统总线接收的测试结果数据进行压缩和存储 测试模式。

    Bus system and method thereof
    4.
    发明申请
    Bus system and method thereof 有权
    总线系统及其方法

    公开(公告)号：US20050204084A1

    公开(公告)日：2005-09-15

    申请号：US11035741

    申请日：2005-01-18

    申请人： Kee-Won Joe ,  Jong-Ho Kim ,  Hae-Young Rha ,  Jong-Chul Shin

    发明人： Kee-Won Joe ,  Jong-Ho Kim ,  Hae-Young Rha ,  Jong-Chul Shin

    IPC分类号： G06F13/36 ,  G06F13/00 ,  G06F13/14 ,  G06F13/16 ,  G06F13/364 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

    CPC分类号： G06F13/364

    摘要： A bus system including a bus arbiter and a plurality of masters. The bus arbiter grants bus control to one of the plurality of masters. When a master with bus control sends a read command, bus control is transferred to another one of the plurality of masters, thereby increasing the efficiency of the bus system. A method including sending a read command and transferring bus control to another one of a plurality of masters before receiving the response to the read command.

    摘要翻译： 一种总线系统，包括总线仲裁器和多个主机。 总线仲裁器将总线控制权授予多个主机之一。 当具有总线控制的主机发送读取命令时，总线控制被传送到多个主机中的另一个，从而提高总线系统的效率。 一种方法，包括在接收对所述读取命令的响应之前发送读取命令并将总线控制传送到多个主机中的另一个主机。

    System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC
    5.
    发明授权
    System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC 失效
    具有内置自检电路的片上系统（SOC）和SOC的自检方法

    公开(公告)号：US07761763B2

    公开(公告)日：2010-07-20

    申请号：US12182785

    申请日：2008-07-30

    申请人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

    发明人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318335

    摘要： A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

    摘要翻译： 提供了具有内置自检（BIST）电路的片上系统（SOC）和SOC的自检方法。 具有BIST电路的SOC包括具有BIST逻辑电路的知识产权（IP）块和BIST控制单元。 BIST逻辑电路响应于通过系统总线接收的控制数据在正常或测试模式下工作，并在测试模式下输出测试结果数据。 BIST控制单元通过系统总线将控制数据，命令信号，测试模式数据和测试地址信号传输到BIST逻辑电路来测试IP模块，并将通过系统总线接收的测试结果数据进行压缩和存储 测试模式。

    SYSTEM-ON-CHIP (SOC) HAVING BUILT-IN-SELF-TEST CIRCUITS AND A SELF-TEST METHOD OF THE SOC
    6.
    发明申请
    SYSTEM-ON-CHIP (SOC) HAVING BUILT-IN-SELF-TEST CIRCUITS AND A SELF-TEST METHOD OF THE SOC 失效
    具有内置自检电路的系统芯片（SOC）和SOC的自检方法

    公开(公告)号：US20080313515A1

    公开(公告)日：2008-12-18

    申请号：US12182785

    申请日：2008-07-30

    申请人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

    发明人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

    IPC分类号： G01R31/3187 ,  G06F11/27

    CPC分类号： G01R31/318335

    摘要： A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

    摘要翻译： 提供了具有内置自检（BIST）电路的片上系统（SOC）和SOC的自检方法。 具有BIST电路的SOC包括具有BIST逻辑电路的知识产权（IP）块和BIST控制单元。 BIST逻辑电路响应于通过系统总线接收的控制数据在正常或测试模式下工作，并在测试模式下输出测试结果数据。 BIST控制单元通过系统总线将控制数据，命令信号，测试模式数据和测试地址信号传输到BIST逻辑电路来测试IP模块，并将通过系统总线接收的测试结果数据进行压缩和存储 测试模式。

    System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC
    7.
    发明授权
    System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC 有权
    具有内置自检电路的片上系统（SOC）和SOC的自检方法

    公开(公告)号：US07421635B2

    公开(公告)日：2008-09-02

    申请号：US11066585

    申请日：2005-02-25

    申请人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

    发明人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318335

    摘要： A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

    摘要翻译： 提供了具有内置自检（BIST）电路的片上系统（SOC）和SOC的自检方法。 具有BIST电路的SOC包括具有BIST逻辑电路的知识产权（IP）块和BIST控制单元。 BIST逻辑电路响应于通过系统总线接收的控制数据在正常或测试模式下工作，并在测试模式下输出测试结果数据。 BIST控制单元通过系统总线将控制数据，命令信号，测试模式数据和测试地址信号传输到BIST逻辑电路来测试IP模块，并将通过系统总线接收的测试结果数据进行压缩和存储 测试模式。

    Bus system with protocol conversion for arbitrating bus occupation and method thereof
    8.
    发明授权
    Bus system with protocol conversion for arbitrating bus occupation and method thereof 有权
    用于仲裁总线占用的协议转换的总线系统及其方法

    公开(公告)号：US07412550B2

    公开(公告)日：2008-08-12

    申请号：US11035741

    申请日：2005-01-18

    申请人： Kee-Won Joe ,  Jong-Ho Kim ,  Hae-Young Rha ,  Jong-Chul Shin

    发明人： Kee-Won Joe ,  Jong-Ho Kim ,  Hae-Young Rha ,  Jong-Chul Shin

    IPC分类号： G06F13/00

    CPC分类号： G06F13/364

    摘要： A bus system including a bus arbiter and a plurality of masters. The bus arbiter grants bus control to one of the plurality of masters. When a master with bus control sends a read command, bus control is transferred to another one of the plurality of masters, thereby increasing the efficiency of the bus system. A method including sending a read command and transferring bus control to another one of a plurality of masters before receiving the response to the read command.

    摘要翻译： 一种总线系统，包括总线仲裁器和多个主机。 总线仲裁器将总线控制权授予多个主机之一。 当具有总线控制的主机发送读取命令时，总线控制被传送到多个主机中的另一个，从而提高总线系统的效率。 一种方法，包括在接收对所述读取命令的响应之前发送读取命令并将总线控制传送到多个主机中的另一个主机。