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    Sliding/folding combination type portable digital communication apparatus and hinge unit thereof
    1.
    发明申请
    Sliding/folding combination type portable digital communication apparatus and hinge unit thereof 审中-公开
    滑动/折叠组合型便携式数字通信设备及其铰链单元

    公开(公告)号：US20060135227A1

    公开(公告)日：2006-06-22

    申请号：US11261892

    申请日：2005-10-28

    申请人： Yu-Chul Chang ,  Jong-Chul Shin ,  Seung-Chul Lee

    发明人： Yu-Chul Chang ,  Jong-Chul Shin ,  Seung-Chul Lee

    IPC分类号： H04M1/00

    CPC分类号： H04M1/0237 ,  H04M1/0216 ,  H04M2250/16

    摘要： Disclosed herein is a sliding/folding combination type portable digital communication apparatus that includes a body; a sliding folder having a first position in which it is constrained on the body, a second position in which it has slid a predetermined distance while continuously facing the body, and a third position in which it has rotated away from the body after the sliding in such a manner that it does not face the body; and a sliding hinge module positioned between the body and the sliding folder to travel together with the sliding folder and provide a force necessary for folding/unfolding the sliding folder. The user can conveniently use a single communication apparatus having the advantages of both sliding-type and folding-type apparatuses.

    摘要翻译： 本文公开了一种滑动/折叠组合型便携式数字通信装置，其包括主体; 具有第一位置的滑动夹具，其被限制在所述主体上;第二位置，其在所述第二位置中在连续面向所述主体的同时已经滑动预定距离;以及第三位置，在所述第三位置中，所述第二位置在滑动之后已经远离所述身体旋转 这样一种不会面对身体的方式; 以及定位在主体和滑动夹具之间的滑动铰链模块，以与滑动夹具一起移动并提供折叠/展开滑动夹具所需的力。 用户可以方便地使用具有滑动型和折叠型装置两者的优点的单个通信装置。

    Data delay control circuit and method
    3.
    发明授权
    Data delay control circuit and method 失效
    数据延迟控制电路及方法

    公开(公告)号：US08305127B2

    公开(公告)日：2012-11-06

    申请号：US12726565

    申请日：2010-03-18

    申请人： Jong-Chul Shin

    发明人： Jong-Chul Shin

    IPC分类号： H03H11/26

    CPC分类号： H03L7/00 ,  H03K3/0315 ,  H03K5/13 ,  H03K2005/00058 ,  H03K2005/00143 ,  H03L7/0805

    摘要： A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal. Consequently, the data delay circuit can automatically generate a data delay signal according to the changes in the operating environment.

    摘要翻译： 一种数据延迟控制电路和方法，其可以自适应地反映诸如工作温度，工作电压和半导体芯片的制造过程的操作环境的变化。 数据延迟控制电路设计成能够在设计半导体芯片时需要预定时间段的预期延迟时适应地延迟数据。 数据延迟电路包括可以反映延迟单元的延迟周期的变化并且自动调整延迟单元的延迟周期的时钟振荡单元。 由于数据延迟电路包括监视电路和多个延迟路径，所以数据延迟电路可以提供具有所需延迟值的延迟路径。 因此，即使当半导体器件的工作环境改变时，数据延迟电路也可以控制数据信号的延迟周期。 因此，数据延迟电路可以根据操作环境的变化自动生成数据延迟信号。

    DATA DELAY CONTROL CIRCUIT AND METHOD
    4.
    发明申请
    DATA DELAY CONTROL CIRCUIT AND METHOD 失效
    数据延迟控制电路及方法

    公开(公告)号：US20100182064A1

    公开(公告)日：2010-07-22

    申请号：US12726565

    申请日：2010-03-18

    申请人： Jong-Chul Shin

    发明人： Jong-Chul Shin

    IPC分类号： H03H11/26

    CPC分类号： H03L7/00 ,  H03K3/0315 ,  H03K5/13 ,  H03K2005/00058 ,  H03K2005/00143 ,  H03L7/0805

    摘要： A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal. Consequently, the data delay circuit can automatically generate a data delay signal according to the changes in the operating environment.

    摘要翻译： 一种数据延迟控制电路和方法，其可以自适应地反映诸如工作温度，工作电压和半导体芯片的制造过程的操作环境的变化。 数据延迟控制电路设计成能够在设计半导体芯片时需要预定时间段的预期延迟时适应地延迟数据。 数据延迟电路包括可以反映延迟单元的延迟周期的变化并且自动调整延迟单元的延迟周期的时钟振荡单元。 由于数据延迟电路包括监视电路和多个延迟路径，所以数据延迟电路可以提供具有所需延迟值的延迟路径。 因此，即使当半导体器件的工作环境改变时，数据延迟电路也可以控制数据信号的延迟周期。 因此，数据延迟电路可以根据操作环境的变化自动生成数据延迟信号。

    Data delay control circuit and method
    5.
    发明授权
    Data delay control circuit and method 失效
    数据延迟控制电路及方法

    公开(公告)号：US07696802B2

    公开(公告)日：2010-04-13

    申请号：US11669296

    申请日：2007-01-31

    申请人： Jong-Chul Shin

    发明人： Jong-Chul Shin

    IPC分类号： H03H11/26

    CPC分类号： H03L7/00 ,  H03K3/0315 ,  H03K5/13 ,  H03K2005/00058 ,  H03K2005/00143 ,  H03L7/0805

    摘要： A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal. Consequently, the data delay circuit can automatically generate a data delay signal according to the changes in the operating environment.

    摘要翻译： 一种数据延迟控制电路和方法，其可以自适应地反映诸如工作温度，工作电压和半导体芯片的制造过程的操作环境的变化。 数据延迟控制电路设计成能够在设计半导体芯片时需要预定时间段的预期延迟时适应地延迟数据。 数据延迟电路包括可以反映延迟单元的延迟周期的变化并且自动调整延迟单元的延迟周期的时钟振荡单元。 由于数据延迟电路包括监视电路和多个延迟路径，所以数据延迟电路可以提供具有所需延迟值的延迟路径。 因此，即使当半导体器件的工作环境改变时，数据延迟电路也可以控制数据信号的延迟周期。 因此，数据延迟电路可以根据操作环境的变化自动生成数据延迟信号。

    System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC
    6.
    发明授权
    System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC 失效
    具有内置自检电路的片上系统（SOC）和SOC的自检方法

    公开(公告)号：US07761763B2

    公开(公告)日：2010-07-20

    申请号：US12182785

    申请日：2008-07-30

    申请人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

    发明人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318335

    摘要： A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

    摘要翻译： 提供了具有内置自检（BIST）电路的片上系统（SOC）和SOC的自检方法。 具有BIST电路的SOC包括具有BIST逻辑电路的知识产权（IP）块和BIST控制单元。 BIST逻辑电路响应于通过系统总线接收的控制数据在正常或测试模式下工作，并在测试模式下输出测试结果数据。 BIST控制单元通过系统总线将控制数据，命令信号，测试模式数据和测试地址信号传输到BIST逻辑电路来测试IP模块，并将通过系统总线接收的测试结果数据进行压缩和存储 测试模式。

    SYSTEM-ON-CHIP (SOC) HAVING BUILT-IN-SELF-TEST CIRCUITS AND A SELF-TEST METHOD OF THE SOC
    7.
    发明申请
    SYSTEM-ON-CHIP (SOC) HAVING BUILT-IN-SELF-TEST CIRCUITS AND A SELF-TEST METHOD OF THE SOC 失效
    具有内置自检电路的系统芯片（SOC）和SOC的自检方法

    公开(公告)号：US20080313515A1

    公开(公告)日：2008-12-18

    申请号：US12182785

    申请日：2008-07-30

    申请人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

    发明人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

    IPC分类号： G01R31/3187 ,  G06F11/27

    CPC分类号： G01R31/318335

    摘要： A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

    摘要翻译： 提供了具有内置自检（BIST）电路的片上系统（SOC）和SOC的自检方法。 具有BIST电路的SOC包括具有BIST逻辑电路的知识产权（IP）块和BIST控制单元。 BIST逻辑电路响应于通过系统总线接收的控制数据在正常或测试模式下工作，并在测试模式下输出测试结果数据。 BIST控制单元通过系统总线将控制数据，命令信号，测试模式数据和测试地址信号传输到BIST逻辑电路来测试IP模块，并将通过系统总线接收的测试结果数据进行压缩和存储 测试模式。

    System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC
    8.
    发明授权
    System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC 有权
    具有内置自检电路的片上系统（SOC）和SOC的自检方法

    公开(公告)号：US07421635B2

    公开(公告)日：2008-09-02

    申请号：US11066585

    申请日：2005-02-25

    申请人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

    发明人： Jong-Chul Shin ,  Jong-Ho Kim ,  Hae-Young Rha ,  Kee-Won Joe

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318335

    摘要： A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

    摘要翻译： 提供了具有内置自检（BIST）电路的片上系统（SOC）和SOC的自检方法。 具有BIST电路的SOC包括具有BIST逻辑电路的知识产权（IP）块和BIST控制单元。 BIST逻辑电路响应于通过系统总线接收的控制数据在正常或测试模式下工作，并在测试模式下输出测试结果数据。 BIST控制单元通过系统总线将控制数据，命令信号，测试模式数据和测试地址信号传输到BIST逻辑电路来测试IP模块，并将通过系统总线接收的测试结果数据进行压缩和存储 测试模式。

    Bus system with protocol conversion for arbitrating bus occupation and method thereof
    9.
    发明授权
    Bus system with protocol conversion for arbitrating bus occupation and method thereof 有权
    用于仲裁总线占用的协议转换的总线系统及其方法

    公开(公告)号：US07412550B2

    公开(公告)日：2008-08-12

    申请号：US11035741

    申请日：2005-01-18

    申请人： Kee-Won Joe ,  Jong-Ho Kim ,  Hae-Young Rha ,  Jong-Chul Shin

    发明人： Kee-Won Joe ,  Jong-Ho Kim ,  Hae-Young Rha ,  Jong-Chul Shin

    IPC分类号： G06F13/00

    CPC分类号： G06F13/364

    摘要： A bus system including a bus arbiter and a plurality of masters. The bus arbiter grants bus control to one of the plurality of masters. When a master with bus control sends a read command, bus control is transferred to another one of the plurality of masters, thereby increasing the efficiency of the bus system. A method including sending a read command and transferring bus control to another one of a plurality of masters before receiving the response to the read command.

    摘要翻译： 一种总线系统，包括总线仲裁器和多个主机。 总线仲裁器将总线控制权授予多个主机之一。 当具有总线控制的主机发送读取命令时，总线控制被传送到多个主机中的另一个，从而提高总线系统的效率。 一种方法，包括在接收对所述读取命令的响应之前发送读取命令并将总线控制传送到多个主机中的另一个主机。

    Keypad assembly for mobile phone
    10.
    发明授权
    Keypad assembly for mobile phone 有权
    键盘组合为手机

    公开(公告)号：US08227715B2

    公开(公告)日：2012-07-24

    申请号：US12696288

    申请日：2010-01-29

    申请人： Jung-Won Park ,  Jong-Chul Shin ,  Jong-Kyun Shin ,  Young-Bae Ji

    发明人： Jung-Won Park ,  Jong-Chul Shin ,  Jong-Kyun Shin ,  Young-Bae Ji

    IPC分类号： H01H9/26

    CPC分类号： H01H13/88 ,  H01H13/83 ,  H01H13/86 ,  H01H2223/04 ,  H01H2229/022 ,  H01H2229/044 ,  H04M1/23

    摘要： A keypad assembly mounted in a portable terminal is disclosed. The keypad assembly has a window keypad including a display window disposed on a front face of the portable terminal. A keypad top is integrally molded with the display window and simultaneously assembled on the front face of the portable terminal, thereby providing an easier assembly than known heretofore, as two parts can be assembled at the same time and additionally provide an elegant exterior front face.

    摘要翻译： 公开了安装在便携式终端中的小键盘组件。 键盘组件具有包括设置在便携式终端的正面上的显示窗口的窗口键盘。 键盘顶部与显示窗一体地模制，同时组装在便携式终端的前表面上，从而提供了比迄今为止更容易的组装，因为两个部件可以同时组装，并且另外提供优雅的外部正面。