公开(公告)号：US20080270050A1

公开(公告)日：2008-10-30

申请号：US12110198

申请日：2008-04-25

Applicant: Jong-Hyun LEE ,  Soo-Yong LEE

Inventor： Jong-Hyun LEE ,  Soo-Yong LEE

IPC: G01R31/26

CPC classification number: G01R31/31935 ,  G01R31/318511 ,  G11C11/41 ,  G11C11/412 ,  G11C29/44 ,  G11C29/50

Abstract: A test system and a failure parsing method. The test system may comprise a cell array including defective cells formed according to various failure causes, a test apparatus configured to measure electric characteristics from the defective cells and make the measured electric characteristics numerical, and a database apparatus configured to store the numerical electric characteristics. The failure parsing method may include forming defective cells to have at least one failure cause, measuring electric characteristics of each of the defective cells, storing the measured electric characteristics of each of the defective cells in a database, and judging failure causes of a failed chip of a semiconductor wafer based on the database.

Abstract translation: 测试系统和故障解析方法。 该测试系统可以包括一个单元阵列，该单元阵列包括根据各种故障原因而形成的缺陷单元，一个被配置为从有缺陷单元测量电特性并使测量的电特性值数值的测试设备，以及被配置为存储数字电特性的数据库设备。 故障解析方法可以包括形成有缺陷的单元以具有至少一个故障原因，测量每个故障单元的电特性，将每个故障单元的测量电特性存储在数据库中，以及判断故障芯片的故障原因 基于数据库的半导体晶片。