Apparatus for measuring in-phase and quadrature (IQ) imbalance
    2.
    发明授权
    Apparatus for measuring in-phase and quadrature (IQ) imbalance 有权
    用于测量同相和正交(IQ)不平衡的装置

    公开(公告)号:US07995645B2

    公开(公告)日:2011-08-09

    申请号:US12027762

    申请日:2008-02-07

    IPC分类号: H04B3/46

    摘要: The present general inventive concept relates to apparatuses and/or methods for measuring an in-phase and quadrature (IQ) imbalance. In one embodiment, a signal generator can provide a first IQ signal of a DC component during a first period and the first IQ signal of a first angular frequency during a second period, an IQ up-conversion mixer can up-convert the first IQ signal by a second angular frequency during the first period and up-convert the first IQ signal by a third angular frequency during the second period to output a second IQ signal, an IQ down-conversion mixer can down-convert the second IQ signal by the third angular frequency to output a third IQ signal and an IQ imbalance detector can obtain a first IQ imbalance (e.g., Rx IQ imbalance) from the third IQ signal during the first period and a second IQ imbalance (e.g., Tx/Rx IQ imbalance) during the second period.

    摘要翻译: 本总体发明构思涉及用于测量同相和正交(IQ)不平衡的装置和/或方法。 在一个实施例中,信号发生器可以在第一周期期间提供DC分量的第一IQ信号,并且在第二周期期间提供第一角频率的第一IQ信号,IQ上变频混频器可以上变频第一IQ信号 在第一周期期间以第二角度频率进行第二角度频率,并且在第二周期期间将第一IQ信号上升转换第三角度频率以输出第二IQ信号,IQ降频转换混频器可以将第二IQ信号下变频第三IQ信号 输出第三IQ信号和IQ不平衡检测器的角频率可以在第一周期期间从第三IQ信号和第二IQ不平衡(例如,Tx / Rx IQ不平衡)获得第一IQ不平衡(例如,Rx IQ不平衡) 第二期。

    Frequency synthesizer using two phase locked loops
    3.
    发明申请
    Frequency synthesizer using two phase locked loops 有权
    频率合成器使用两个锁相环

    公开(公告)号:US20080197891A1

    公开(公告)日:2008-08-21

    申请号:US11902358

    申请日:2007-09-20

    IPC分类号: H03L7/22 H03B21/01

    CPC分类号: H03L7/23 H03L7/183 H03L7/1976

    摘要: The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and the second output frequency.

    摘要翻译: 本申请公开了与频率合成器相关的系统和方法实施例。 频率合成器的实施例可以具有低相位噪声和窄通道间隔。 频率合成器的实施例可以使用两个锁相环。 频率合成器的一个实施例可以包括:参考频率振荡器,用于输出具有参考频率的信号,整数N个锁相环,以基于参考频率信号产生第一输出频率信号;分数N相锁相环 基于参考频率信号产生第二输出频率,以及通过组合第一输出频率和第二输出频率来产生输出频率信号的电路。

    Tranceiver circuit for compensating IQ mismatch and carrier leakage and method for controlling the same
    4.
    发明申请
    Tranceiver circuit for compensating IQ mismatch and carrier leakage and method for controlling the same 有权
    用于补偿IQ失配和载波泄漏的收发器电路及其控制方法

    公开(公告)号:US20070202812A1

    公开(公告)日:2007-08-30

    申请号:US11708705

    申请日:2007-02-21

    IPC分类号: H04B1/38 H04B1/40

    CPC分类号: H04B1/525

    摘要: Embodiments of methods, transceiver circuits, and systems can compensate an IQ mismatch (e.g., Tx or Rx) or a carrier leakage using a plurality of local oscillators. One embodiment of a transceiver can include a first up-conversion IQ mixer, a second up-conversion IQ mixer, a first down-conversion IQ mixer with an input to receive an output of the second up-conversion IQ mixer, a second down-conversion IQ mixer with an input to receive an output of the first up-conversion IQ mixer, a first local oscillator to generate a first IQ LO signal for the first up-conversion IQ mixer and the first down-conversion IQ mixer, and a second local oscillator to generate a second IQ LO signal for the second up-conversion IQ mixer and the second down-conversion IQ mixer.

    摘要翻译: 方法,收发器电路和系统的实施例可以使用多个本地振荡器补偿IQ失配(例如,Tx或Rx)或载波泄漏。 收发器的一个实施例可以包括第一上变频IQ混频器,第二上变频IQ混频器,具有用于接收第二上变频IQ混频器的输出的输入的第一下变频IQ混频器, 转换IQ混频器,具有用于接收第一上变频IQ混频器的输出的输入端,第一本地振荡器,用于产生用于第一上变频IQ混频器和第一下变频IQ混频器的第一IQ LO信号,以及第二本地振荡器 本地振荡器产生用于第二上变频IQ混频器和第二下变频IQ混频器的第二IQ LO信号。

    Adaptive linearization technique for communication building block

    公开(公告)号:US07002410B2

    公开(公告)日:2006-02-21

    申请号:US10229267

    申请日:2002-08-28

    IPC分类号: H03F1/26

    CPC分类号: H03F1/3223 H03F1/3229

    摘要: The present invention is directed to a linearization apparatus and method. Preferred embodiments according to the present invention can combine an auxiliary non-linear block to a functional block of a system to increase linearity of an output signal of the system such as a communication system. System overhead due to the non-linear auxiliary block can be small because of circuit structure, cost and low consumption. Further, the non-linear auxiliary block can be designed so that no feedback path is required. Further preferred embodiments can use a feedback path without loss of stability by using a cancellation apparatus or process based on an averaging detection of the output signal. For example, a feedback loop can detect power leakage in a sideband caused by non-linearities of the communication system.

    Tranceiver circuit for compensating IQ mismatch and carrier leakage and method for controlling the same
    6.
    发明授权
    Tranceiver circuit for compensating IQ mismatch and carrier leakage and method for controlling the same 有权
    用于补偿IQ失配和载波泄漏的收发器电路及其控制方法

    公开(公告)号:US07831215B2

    公开(公告)日:2010-11-09

    申请号:US11708705

    申请日:2007-02-21

    IPC分类号: H04B1/40

    CPC分类号: H04B1/525

    摘要: Embodiments of methods, transceiver circuits, and systems can compensate an IQ mismatch (e.g., Tx or Rx) or a carrier leakage using a plurality of local oscillators. One embodiment of a transceiver can include a first up-conversion IQ mixer, a second up-conversion IQ mixer, a first down-conversion IQ mixer with an input to receive an output of the second up-conversion IQ mixer, a second down-conversion IQ mixer with an input to receive an output of the first up-conversion IQ mixer, a first local oscillator to generate a first IQ LO signal for the first up-conversion IQ mixer and the first down-conversion IQ mixer, and a second local oscillator to generate a second IQ LO signal for the second up-conversion IQ mixer and the second down-conversion IQ mixer.

    摘要翻译: 方法,收发器电路和系统的实施例可以使用多个本地振荡器补偿IQ失配(例如,Tx或Rx)或载波泄漏。 收发器的一个实施例可以包括第一上变频IQ混频器,第二上变频IQ混频器,具有用于接收第二上变频IQ混频器的输出的输入的第一下变频IQ混频器, 转换IQ混频器,具有用于接收第一上变频IQ混频器的输出的输入端,第一本地振荡器,用于产生用于第一上变频IQ混频器和第一下变频IQ混频器的第一IQ LO信号,以及第二本地振荡器 本地振荡器产生用于第二上变频IQ混频器和第二下变频IQ混频器的第二IQ LO信号。

    Low noise amplifier having improved linearity
    7.
    发明授权
    Low noise amplifier having improved linearity 有权
    低噪声放大器具有改善的线性度

    公开(公告)号:US07812672B2

    公开(公告)日:2010-10-12

    申请号:US11976911

    申请日:2007-10-29

    IPC分类号: H03F3/30

    摘要: Embodiments of the present general inventive concept include a low noise amplifier and method with an improved linearity while reducing a noise disadvantage (e.g., increase). One embodiment of a low noise amplifier can include a first transistor to receive an input signal at a control terminal thereof, a second transistor having a first terminal coupled to a second terminal of the first transistor, an envelope detector to output a control signal corresponding to a characteristic of the input signal and an envelope amplifier to amplify the control signal to be applied to a control terminal of the second transistor.

    摘要翻译: 本发明总体构思的实施例包括具有改善的线性度的低噪声放大器和方法,同时降低噪声不利(例如增加)。 低噪声放大器的一个实施例可以包括在其控制端接收输入信号的第一晶体管,具有耦合到第一晶体管的第二端的第一端的第二晶体管,用于输出对应于 输入信号的特性和包络放大器,放大要施加到第二晶体管的控制端的控制信号。

    Frequency synthesizer using two phase locked loops
    8.
    发明授权
    Frequency synthesizer using two phase locked loops 有权
    频率合成器使用两个锁相环

    公开(公告)号:US07560960B2

    公开(公告)日:2009-07-14

    申请号:US11902358

    申请日:2007-09-20

    IPC分类号: H03B21/00

    CPC分类号: H03L7/23 H03L7/183 H03L7/1976

    摘要: The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and the second output frequency.

    摘要翻译: 本申请公开了与频率合成器相关的系统和方法实施例。 频率合成器的实施例可以具有低相位噪声和窄通道间隔。 频率合成器的实施例可以使用两个锁相环。 频率合成器的一个实施例可以包括:参考频率振荡器,用于输出具有参考频率的信号,整数N个锁相环,以基于参考频率信号产生第一输出频率信号;分数N相锁相环 基于参考频率信号产生第二输出频率,以及通过组合第一输出频率和第二输出频率来产生输出频率信号的电路。

    System and method for tuning a frequency generator using an LC oscillator
    10.
    发明授权
    System and method for tuning a frequency generator using an LC oscillator 有权
    使用LC振荡器调谐频率发生器的系统和方法

    公开(公告)号:US07512390B2

    公开(公告)日:2009-03-31

    申请号:US11057414

    申请日:2005-02-15

    IPC分类号: H04B7/00 H04B1/181

    摘要: An LC-VCO includes a multivibrator which outputs a frequency signal, a fine tuning circuit which tunes the frequency signal by a first amount, a coarse tuning circuit which tunes the frequency signal by a second amount, and a control circuit which controls the fine and coarse tuning circuits. The coarse tuning circuit is formed from one or more capacitive arrays and the fine tuning circuit is formed from one or more varactors. The capacitive arrays are preferably controlled by a digital signal, where each bit selectively couples a respective capacitor to the multivibrator. An analog signal controls the value of the varactors. The capacitive arrays and varactors charge and discharge an inducator in the multivibrator to tune the frequency signal. The VCO may be incorporated within a phase-locked loop, where the capacitors may be assigned different weight and/or redundancy values to tune an output frequency signal. In one embodiment, coarse tuning and lead-lag detection is performed more accurately to allow the size of the varactors to become significantly reduced compared with other circuits which have been proposed.

    摘要翻译: LC-VCO包括输出频率信号的多谐振荡器,将频率信号调谐第一量的微调电路,将频率信号调谐第二量的粗调谐电路,以及控制电路, 粗调电路。 粗调谐电路由一个或多个电容阵列形成,并且微调电路由一个或多个变容二极管形成。 电容阵列优选地由数字信号控制,其中每个位选择性地将相应的电容器耦合到多谐振荡器。 模拟信号控制变容二极管的值。 电容阵列和变容二极管对多谐振荡器中的感应器充电和放电,以调谐频率信号。 VCO可以并入在锁相环中,其中电容器可被分配不同的权重和/或冗余值来调谐输出频率信号。 在一个实施例中,与已经提出的其他电路相比,更精确地执行粗调和超前滞后检测,以允许变容二极管的尺寸显着降低。