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    Method for designing an integrated circuit having multiple voltage domains
    1.
    发明授权
    Method for designing an integrated circuit having multiple voltage domains 失效
    用于设计具有多个电压域的集成电路的方法

    公开(公告)号：US07000214B2

    公开(公告)日：2006-02-14

    申请号：US10707068

    申请日：2003-11-19

    申请人： Joseph A. Iadanza ,  Raminderpal Singh ,  Sebastian T. Ventrone ,  Ivan L. Wemple

    发明人： Joseph A. Iadanza ,  Raminderpal Singh ,  Sebastian T. Ventrone ,  Ivan L. Wemple

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.

    摘要翻译： 一种用于设计具有多个电压域的集成电路的方法，包括：（a）从包含在高级设计文件中的信息，定义全局连接声明和电压域连接声明的高级设计文件生成逻辑集成电路设计; （b）基于逻辑集成电路设计，优选组件文件中的信息和电压域定义文件中的信息，将逻辑集成电路设计合成为合成集成电路设计; （c）基于电压域定义文件和设计约束文件中的信息从合成的集成电路设计中产生噪声模型; 和（d）根据设计约束文件中的约束和电路级配置文件中的约束模拟噪声模型，以确定合成的集成电路设计是否满足预定的噪声模拟目标。

    Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits
    2.
    发明授权
    Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits 有权
    用于将全局时钟选通电路转换为本地时钟门控电路的方法和装置

    公开(公告)号：US07257788B2

    公开(公告)日：2007-08-14

    申请号：US10904397

    申请日：2004-11-08

    申请人： Allen P. Haar ,  Joseph A. Iadanza ,  Sebastian T. Ventrone ,  Ivan L. Wemple

    发明人： Allen P. Haar ,  Joseph A. Iadanza ,  Sebastian T. Ventrone ,  Ivan L. Wemple

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5045

    摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

    摘要翻译： 公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。 最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。 根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。 在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

    Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design
    4.
    发明授权
    Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design 失效
    在设计，合成和物理设计过程中，降噪/减少/减少Di / Dt的转换平衡

    公开(公告)号：US07643591B2

    公开(公告)日：2010-01-05

    申请号：US11460065

    申请日：2006-07-26

    申请人： Igor Arsovski ,  Serafino Bueti ,  Joseph A. Iadanza ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Serafino Bueti ,  Joseph A. Iadanza ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

    IPC分类号： H04L7/00

    CPC分类号： H04L7/02

    摘要： A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.

    摘要翻译： 一种用于噪声的方法，包括合成诸如流水线电路架构或时钟域的顺序锁存器的块，其包括组合逻辑，合成根或主时钟以及用于每个块的至少一个相移子域时钟， 输入和主输出到根时钟，将块的非主输入和非主输出分配给子域时钟，将根时钟输入分为根时钟输入和相移子域时钟输入， 为每个块分配不同的相移子域时钟相位偏移，为根时钟和相移子域时钟创建时钟产生电路。

    Skewed Double Differential Pair Circuit for Offset Cancelllation
    5.
    发明申请
    Skewed Double Differential Pair Circuit for Offset Cancelllation 有权
    用于偏移消除的偏斜双差分电路

    公开(公告)号：US20090261882A1

    公开(公告)日：2009-10-22

    申请号：US12494642

    申请日：2009-06-30

    申请人： Igor Arsovski ,  Anthony R. Bonaccio ,  Hayden (Clay) Cranford, JR. ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone ,  Benjamin T. Voegeli

    发明人： Igor Arsovski ,  Anthony R. Bonaccio ,  Hayden (Clay) Cranford, JR. ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone ,  Benjamin T. Voegeli

    IPC分类号： H03L5/00

    CPC分类号： H03K19/09432 ,  H03K19/018528

    摘要： A differential system producing differential signals with offset cancellation utilizing a double differential input pair system is disclosed. It uses two parallel differential transistor pairs which are intentionally skewed. Nominally, the differential pairs are skewed in opposite direction from each, but with equal magnitude, so that the combination of the two differential pairs is nominally balanced. The current through each differential pair is then increased or decreased until any offset is sufficiently cancelled, using a selection means for providing an equi-potential value to first and second differential inputs in a calibration mode of the system and a comparison means for comparing first and second differential outputs in a calibration mode to determine the offset of the system.

    摘要翻译： 公开了一种使用双差分输入对系统产生具有偏移消除的差分信号的差分系统。 它使用两个有意偏斜的并联差分晶体管对。 名义上，差分对在每个方向相反的方向上倾斜，但是具有相等的幅度，使得两个差分对的组合被名义上平衡。 然后，使用用于在系统的校准模式中为第一和第二差分输入提供等电位值的选择装置，增加或减少通过每个差分对的电流，直到任何偏移被充分抵消为止，以及用于比较第一和第 第二差分输出在校准模式下确定系统的偏移。

    System and method for balancing delay of signal communication paths through well voltage adjustment
    10.
    发明授权
    System and method for balancing delay of signal communication paths through well voltage adjustment 有权
    通过井电压调整来平衡信号通信路径的延迟的系统和方法

    公开(公告)号：US07404114B2

    公开(公告)日：2008-07-22

    申请号：US10906343

    申请日：2005-02-15

    申请人： Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone

    发明人： Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone

    IPC分类号： G01R31/28

    CPC分类号： H03K5/133 ,  H03K2005/00032

    摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.

    摘要翻译： 在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。 通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。 将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压 在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。