利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

30 条记录 (耗时 0.032 秒)

    Method and apparatus for responding to access errors in a data processing system
    5.
    发明授权
    Method and apparatus for responding to access errors in a data processing system 有权
    用于在数据处理系统中响应访问错误的方法和装置

    公开(公告)号：US07278062B2

    公开(公告)日：2007-10-02

    申请号：US10339022

    申请日：2003-01-09

    申请人： William C. Moyer ,  Michael D. Fitzsimmons ,  Brian M. Millar ,  John J. Vaglica

    发明人： William C. Moyer ,  Michael D. Fitzsimmons ,  Brian M. Millar ,  John J. Vaglica

    IPC分类号： G06F11/00

    CPC分类号： G06F11/004 ,  G06F11/0745 ,  G06F11/0751 ,  G06F11/0793

    摘要： In one embodiment, a data processing system (10) has a processor (14) coupled to a bus, where the data processing system (10) includes access error detection circuitry (26) and access error response circuitry (12), each coupled to the bus (58, 60). The access error detection circuitry detects an access error in the data processing system. The access error response circuitry initiates replacement of an existing value on the bus with a predetermined value when the access error has been detected, and continues to replace the existing value on the bus with the predetermined value when the access error has been detected and a persistent mode indicator has been asserted. The predetermined value may correspond to a predetermined instruction value (74) or a predetermined data value (76). In one embodiment, different values for the predetermined value may be used depending on the current operating mode of the data processing system.

    摘要翻译： 在一个实施例中，数据处理系统（10）具有耦合到总线的处理器（14），其中数据处理系统（10）包括访问错误检测电路（26）和访问错误响应电路（12），每个耦合到 公共汽车（58,60）。 访问错误检测电路检测数据处理系统中的访问错误。 当检测到访问错误时，访问错误响应电路以预定值启动总线上的现​​有值的替换，并且当已经检测到访问错误时，继续以预定值替换总线上的现​​有值，并且持续 模式指示器已被断言。 预定值可以对应于预定指令值（74）或预定数据值（76）。 在一个实施例中，可以根据数据处理系统的当前操作模式使用预定值的不同值。

    Communication steering for use in a multi-master shared resource system
    8.
    发明授权
    Communication steering for use in a multi-master shared resource system 有权
    用于多主共享资源系统的通信指导

    公开(公告)号：US07802038B2

    公开(公告)日：2010-09-21

    申请号：US12276038

    申请日：2008-11-21

    申请人： Ryan D. Bedwell ,  Arnold R. Cruz ,  John J. Vaglica ,  William C. Moyer

    发明人： Ryan D. Bedwell ,  Arnold R. Cruz ,  John J. Vaglica ,  William C. Moyer

    IPC分类号： G06F13/00

    CPC分类号： G06F13/364

    摘要： New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

    摘要翻译： 需要用于在多个主机（12,14）和一个或多个共享资源（24,30,100）之间提供通信的新方法。 可能需要共享的资源的一个例子是符合通用串行总线（USB）标准（100）的电路。 USB规范将USB端点定义为位于USB设备中的数据和控制通道。 在一些情况下，期望具有由一个处理器控制的一定数量的端点以及由不同处理器控制的其他端点，从而提供对所有端点的共享控制。 电路（402,417,480）可用于为诸如中断的附加信号提供转向。 其他共享资源（24,30）可以使用更集中的电路（36）来执行附加信号的转向功能。

    Integrated circuit microprocessor with programmable chip select logic
    9.
    发明授权
    Integrated circuit microprocessor with programmable chip select logic 失效
    具有可编程芯片选择逻辑的集成电路微处理器

    公开(公告)号：US5448744A

    公开(公告)日：1995-09-05

    申请号：US432423

    申请日：1989-11-06

    申请人： James B. Eifert ,  John J. Vaglica ,  James C. Smallwood ,  Mark W. McDermott ,  Hiroyuki Sugiyama ,  William P. LaViolette ,  Bradley G. Burgess

    发明人： James B. Eifert ,  John J. Vaglica ,  James C. Smallwood ,  Mark W. McDermott ,  Hiroyuki Sugiyama ,  William P. LaViolette ,  Bradley G. Burgess

    IPC分类号： G06F9/38 ,  G06F9/22 ,  G06F13/10

    CPC分类号： G06F9/3877

    摘要： An integrated circuit microprocessor has on-board programmable chip select logic. Each of several chip select outputs is individually programmable by means of one or more control register bit fields. For instance, each chip select is asserted for bus cycles within an address range whose starting address and block size are both programmable. In addition, each chip select can be programmed to be active on read cycles only, on write cycles only, or on both read and write cycles. Each chip select can be programmed to be active during interrupt acknowledge cycles only if the interrupt being acknowledged has the same priority level as has been programmed for that chip select. In addition, the timing of the assertion of each chip select is programmable to coincide with either the address strobe or data strobe of the bus cycle. The chip select logic is designed so that it is configured to come out of reset by producing an active chip select signal during the first bus cycle run by the processor following the reset. This chip select is appropriate for selecting a boot ROM, and may later be re-programmed for other use. The chip select logic is capable of supporting cycle-by-cycle dynamic bus sizing by asserting appropriate cycle termination signals. The chip select logic can also insert a programmable number of wait states into a bus cycle to accommodate slow peripherals or can cause a fast termination of a bus cycle to improve the utilization of fast peripherals.

    摘要翻译： 集成电路微处理器具有板载可编程芯片选择逻辑。 几个芯片选择输出中的每一个可以通过一个或多个控制寄存器位字段单独编程。 例如，每个芯片选择在起始地址和块大小均可编程的地址范围内被断言用于总线周期。 此外，每个芯片选择都可以被编程为仅在读周期有效，仅在写周期或读周期和写周期。 只有在确认中断与该芯片选择相同的优先级时，每个芯片选择才能在中断确认周期内被编程为有效。 此外，每个芯片选择的断言的定时可编程为与总线周期的地址选通或数据选通一致。 芯片选择逻辑被设计为使得其被配置为在复位之后由处理器运行的第一总线周期期间产生有效芯片选择信号而退出复位。 该芯片选择适用于选择引导ROM，然后可以重新编程以供其他使用。 芯片选择逻辑能够通过断言适当的周期终止信号来支持逐周期动态总线大小调整。 芯片选择逻辑还可以将可编程的等待状态数插入总线周期以适应慢速外设，或者可能导致总线周期的快速终止，从而提高快速外设的利用率。