公开(公告)号：US20130138930A1

公开(公告)日：2013-05-30

申请号：US13307303

申请日：2011-11-30

Applicant: PETER J. WILSON

Inventor： PETER J. WILSON

IPC: G06F9/30 ,  G06F9/44

CPC classification number: G06F9/546 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3828 ,  G06F9/3851 ,  G06F9/3869

Abstract: Systems and methods are disclosed that include a plurality of processing units having a plurality of register file entries. Control logic identifies a first register entry as including a message address in response to receiving a first instruction. The control logic further identifies a second register entry to receive messages in response to receiving a second instruction.

Abstract translation: 公开了包括具有多个寄存器文件条目的多个处理单元的系统和方法。 响应于接收到第一指令，控制逻辑将第一寄存器条目识别为包括消息地址。 响应于接收到第二指令，控制逻辑进一步识别第二寄存器条目以接收消息。

公开(公告)号：US06940818B2

公开(公告)日：2005-09-06

申请号：US09888425

申请日：2001-06-26

Applicant: Paul J Moran ,  Peter J Wilson ,  David J Law

Inventor： Paul J Moran ,  Peter J Wilson ,  David J Law

IPC: H04L12/801 ,  H04L12/819 ,  H04L12/26 ,  H04L12/56

CPC classification number: H04L47/10 ,  H04L47/215

Abstract: Traffic through a port of a network switch is monitored and controlled by a token bucket system having a duplex mode in which the bandwidths available for incoming and outgoing packets are controlled by a single token bucket and a half-duplex mode in which the bandwidths for incoming and outgoing packets are controlled by a respective one of two token buckets.

Abstract translation: 通过网络交换机的端口的流量由具有双工模式的令牌桶系统监视和控制，其中可用于传入和传出数据包的带宽由单个令牌桶和半双工模式控制，其中传入的带宽 并且输出分组由两个令牌桶中的相应的一个来控制。

公开(公告)号：US06541254B1

公开(公告)日：2003-04-01

申请号：US09685844

申请日：2000-10-10

Applicant: Peter J. Wilson ,  Charles Phillip Morris ,  Donald Stewart Anson ,  Teresa Occhiodoro ,  Julie Bielicki ,  Peter Roy Clements ,  John Joseph Hopwood

Inventor： Peter J. Wilson ,  Charles Phillip Morris ,  Donald Stewart Anson ,  Teresa Occhiodoro ,  Julie Bielicki ,  Peter Roy Clements ,  John Joseph Hopwood

IPC: C12N510

CPC classification number: C12N9/16 ,  A61K38/00

Abstract: The present invention provides a highly glycosylated iduronate-2-sulfatase enzyme comprising an iduronate-2-sulfatase polypeptide with at least 5 kilodalton (kDa) more sugar than iduronate-2-sulfatase purified from a natural source, e.g. human liver. The present invention also provides an enzymatically active polypeptide fragment or variant of such a highly glycosylated iduronate-2-sulfatase. The present invention further provides an isolated nucleic acid encoding iduronate-2-sulfatase, as well as an expression vector, a host cell and a method for producing the present highly glycosylated iduronate-2-sulfatase enzyme. In one embodiment the present invention is directed to a method for producing a glycosylated iduronate-2-sulfatase enzyme which comprises culturing a host cell containing a nucleic acid encoding an enzymatically active iduronate-2-sulfatase polypeptide wherein the host cell glycosylates the polypeptide to a greater degree than a native iduronate-2-sulfatase polypeptide expressed by a natural human liver cell.

Abstract translation: 本发明提供了高度糖基化的糖尿病2-硫酸酯酶，其包含与天然来源例如纯化的伊曲膦酸酯-2-硫酸酯酶相比，具有至少5千道尔顿（kDa）多糖的伊万二酸-2-硫酸酯酶多肽。 人肝。 本发明还提供了这样一种高度糖基化的阿魏酸-2-硫酸酯酶的酶活性多肽片段或变体。 本发明还提供了编码艾杜糖醛酸-2-硫酸酯酶的分离的核酸，以及表达载体，宿主细胞和用于制备本发明的高度糖基化的阿拉伯糖酸-2-硫酸酯酶的方法。 在一个实施方案中，本发明涉及一种生产糖基化的阿魏酸-2-硫酸酯酶的方法，其包括培养含有编码酶活性的阿魏酸-2-硫酸酯酶多肽的核酸的宿主细胞，其中宿主细胞将多肽糖基化成 比由天然人肝细胞表达的天然异二烯酸2-硫酸酯酶多肽更大程度。

公开(公告)号：US4601031A

公开(公告)日：1986-07-15

申请号：US545082

申请日：1983-10-24

Applicant: Christopher P. H. Walker ,  Peter J. Wilson

Inventor： Christopher P. H. Walker ,  Peter J. Wilson

IPC: G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10 ,  G06F11/22

CPC classification number: G11C29/822 ,  G11C29/846

Abstract: The individual rows of a ROM array are accessed by a row decoder/driver in response to the arrival of the address of the individual row on the address lines. A plurality of programmable switches store the address of a row of ROM array found to contain one or more defects. If the incoming address is that of the defective row each of a plurality of comparators connected to both an address line and the associated switch outputs a coincidence signal to an AND gate. The output of the AND gate accesses a spare row of RAM which thus replaces the defective row of the ROM array. Access to the spare row is automatic upon receipt of the address of the defective row. Each column of the ROM array contains a check bit computed from the remaining contents of the respective column, and the data to be stored in the spare row is generated from the remaining contents of the ROM array. At initialization, the generated data which should have been stored in the defective row is written into the spare row.

Abstract translation: 响应于地址线上单独行的地址的到达，ROM阵列的各行被行解码器/驱动器访问。 多个可编程开关存储发现包含一个或多个缺陷的ROM阵列行的地址。 如果输入地址是有缺陷的行，则连接到地址线和相关联的开关的多个比较器中的每一个输出与“和”门的一致信号。 与门的输出访问RAM的备用行，从而代替ROM阵列的有缺陷的行。 在接收到有缺陷的行的地址时，对备用行的访问是自动的。 ROM阵列的每列包含从各列的剩余内容计算的校验位，并且从ROM阵列的剩余内容生成要存储在备用行中的数据。 在初始化时，应该将存储在缺陷行中的生成数据写入备用行。

公开(公告)号：US09092647B2

公开(公告)日：2015-07-28

申请号：US13789387

申请日：2013-03-07

Applicant: Joseph C. Circello ,  Daniel M. McCarthy ,  John D. Mitchell ,  Peter J. Wilson ,  John J. Vaglica

Inventor： Joseph C. Circello ,  Daniel M. McCarthy ,  John D. Mitchell ,  Peter J. Wilson ,  John J. Vaglica

IPC: G06F21/74 ,  G06F7/04

CPC classification number: G06F21/85 ,  G06F12/1458 ,  G06F21/74

Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.

Abstract translation: 可以对可以被配置为在特定安全模式（例如具有一个或多个信道的直接存储器访问（DMA））中作为主机的设备的存储位置进行编程，以指示当被配置为 作为主设备运行。

公开(公告)号：US20140321185A1

公开(公告)日：2014-10-30

申请号：US13873998

申请日：2013-04-30

Applicant: Perry H. Pelley ,  Peter J. Wilson

Inventor： Perry H. Pelley ,  Peter J. Wilson

IPC: G11C5/02 ,  G11C5/06

CPC classification number: G11C5/025 ,  G11C5/02 ,  G11C7/1075 ,  G11C8/16

Abstract: A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks.

Abstract translation: 存储器簇包括布置成具有中心孔的第一块，第二块，第三块和第四块，其中第一块，第二块，第三块和第四块每个都具有第一端口，第二端口， 第三个港口和第四个港口。 第一芯在中心孔中，耦合到第一，第二，第三和第四块中的每一个的第一端口。 第二芯在与第一，第二，第三和第四块中的每一个的第二端口连接的中心孔中。 第三芯在中心孔中，连接到第一，第二，第三和第四块中的每一个的第三端口。 中心孔中的第四个核心耦合到第一，第二，第三和第四块中的每一个的第四端口。

公开(公告)号：US08861243B1

公开(公告)日：2014-10-14

申请号：US13873998

申请日：2013-04-30

Applicant: Perry H. Pelley ,  Peter J. Wilson

Inventor： Perry H. Pelley ,  Peter J. Wilson

IPC: G11C5/02 ,  G11C5/06

CPC classification number: G11C5/025 ,  G11C5/02 ,  G11C7/1075 ,  G11C8/16

Abstract: A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks.

Abstract translation: 存储器簇包括布置成具有中心孔的第一块，第二块，第三块和第四块，其中第一块，第二块，第三块和第四块每个都具有第一端口，第二端口， 第三个港口和第四个港口。 第一芯在中心孔中，耦合到第一，第二，第三和第四块中的每一个的第一端口。 第二芯在与第一，第二，第三和第四块中的每一个的第二端口连接的中心孔中。 第三芯在中心孔中，连接到第一，第二，第三和第四块中的每一个的第三端口。 中心孔中的第四个核心耦合到第一，第二，第三和第四块中的每一个的第四端口。

公开(公告)号：US06472694B1

公开(公告)日：2002-10-29

申请号：US09910022

申请日：2001-07-23

Applicant: Peter J. Wilson ,  Mihir A. Pandya

Inventor： Peter J. Wilson ,  Mihir A. Pandya

IPC: H01L2128

CPC classification number: H01L27/0688 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258 ,  H01L27/0605

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Mixed technology structures are provided in which a microprocessor is formed entirely in a monocrystalline compound semiconductor material layer overlying the silicon substrate. A microprocessor is also provided utilizing portions of the silicon substrate and the monocrystalline compound semiconductor material layer.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 提供了混合技术结构，其中微处理器完全形成在覆盖硅衬底的单晶化合物半导体材料层中。 还提供利用硅衬底和单晶化合物半导体材料层的部分的微处理器。

公开(公告)号：US06470025B1

公开(公告)日：2002-10-22

申请号：US09241477

申请日：1999-02-02

Applicant: Peter J. Wilson ,  Paul J. Moran

Inventor： Peter J. Wilson ,  Paul J. Moran

IPC: H04J302

CPC classification number: H04L12/4641 ,  H04L43/0876 ,  H04L43/16 ,  H04L47/10 ,  H04L47/12 ,  H04L47/13 ,  H04L47/21 ,  H04L47/70 ,  H04L47/745

Abstract: A method of controlling access to a common physical data transmission link from a multiplicity members of a packet-based local area network, wherein the members are partitioned into a plurality of virtual local area networks (VLANs) and wherein packets are identified according to the virtual local area network from which they come, comprises (a) monitoring packet traffic from the virtual local area networks on the link and thereby obtaining measures of the traffic flow from each of the virtual local area networks; (b) determining whether the traffic flow for each respective VLAN is above or below a threshold; (c) denoting a VLAN which is above its threshold as in a restricted state and denoting a VLAN which is below its threshold as in a priority state; (d) arbitrating between requests from the VLANs to transmit data packets on the link; and (e) according priority in the arbitration to a VLAN which is in a priority state over any VLAN which is in a restricted state. A request to transmit is gated with a signal denoting the state of the respective VLAN to provide a set of priority requests. In response to the presence of any priority request the arbitration is made only in respect of the set of priority requests and in the absence of a priority request arbitration is made in respect of the VLANs which indicate a request to transmit. A ‘leaky bucket’ counter may be used for monitoring the traffic for each VLAN.

Abstract translation: 一种从基于分组的局域网的多个成员控制对公共物理数据传输链路的访问的方法，其中所述成员被划分成多个虚拟局域网（VLAN），并且其中分组根据虚拟 它们来自的局域网包括：（a）监视来自链路上的虚拟局域网的分组业务，从而获得每个虚拟局域网的流量的测量; （b）确定每个相应VLAN的业务流量是否高于或低于阈值; （c）表示处于受限状态的VLAN高于阈值的VLAN，并将低于其阈值的VLAN表示为优先级状态; （d）在VLAN之间进行仲裁以在链路上传输数据包; 以及（e）根据处于受限制状态的VLAN处于优先级状态的VLAN的仲裁优先级。 通过表示相应VLAN的状态的信号来选择发送请求以提供一组优先级请求。 响应于存在任何优先权请求，仅针对该组优先级请求进行仲裁，并且在没有优先级请求的情况下，就表示发送请求的VLAN进行仲裁。 “泄漏桶”计数器可用于监控每个VLAN的流量。

公开(公告)号：US06295616B1

公开(公告)日：2001-09-25

申请号：US09179197

申请日：1998-10-27

Applicant: Anne G. O'Connell ,  Peter J. Wilson

Inventor： Anne G. O'Connell ,  Peter J. Wilson

IPC: G01R3128

CPC classification number: H04L49/9073 ,  H04L43/50 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L2012/5628 ,  H04Q11/0478

Abstract: A method of processing data contained in data packets comprises storing a set of microcode instructions of which some are test instructions prescribing a respective test between a data pattern in a packet and a test pattern; defining by means of bit masks a respective multiplicity of programs each consisting a group of instructions selected from the said set of instructions; providing a particular one of said bit masks; reading out from storage the selected group of instructions in the program defined by said particular one of said bit masks, said selected group including at least one of said test instructions; and executing the instructions in the selected group on data packets. Matches between data patterns in said packets and a test pattern defined by said at least one test instruction may be detected. The invention preferably includes reading buffer data and applying to data packets appearing sequentially in the data a selected group of said instructions which independently test data of the data packets in turn.

Abstract translation: 一种处理包含在数据分组中的数据的方法包括存储一组微代码指令，其中一些是在分组中的数据模式和测试模式之间规定相应测试的测试指令; 通过位掩码定义相应的多个程序，每个程序包括从所述指令集中选择的一组指令; 提供所述位掩码中的特定一个; 从存储器中读出由所述位掩码中的所述特定一个定义的程序中的所选择的指令组，所述选择的组包括所述测试指令中的至少一个; 并在数据分组上执行所选组中的指令。 可以检测所述分组中的数据模式与由所述至少一个测试指令定义的测试模式之间的匹配。 本发明优选地包括读取缓冲器数据并且应用于在所述数据中顺序出现的数据，所述数据分组依次独立地测试数据分组的数据。