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    Automated system and processing for expedient diagnosis of broken shift registers latch chains
    3.
    发明授权
    Automated system and processing for expedient diagnosis of broken shift registers latch chains 有权
    自动化系统和处理方便诊断破碎的移位寄存器锁链

    公开(公告)号：US07908532B2

    公开(公告)日：2011-03-15

    申请号：US12032655

    申请日：2008-02-16

    申请人： Joseph Eckelman ,  Donato O. Forlenza ,  Orazio P. Forlenza ,  Robert B. Gass ,  Phong T. Tran

    发明人： Joseph Eckelman ,  Donato O. Forlenza ,  Orazio P. Forlenza ,  Robert B. Gass ,  Phong T. Tran

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318544 ,  G01R31/318536

    摘要： This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.

    摘要翻译： 本发明涉及使用JTAG功能测试模式和执行者来解决在所有锁存系统端口中以串行或侧向宽边插入方式诊断断层扫描链的问题，并且有效地分析响应数据以便容易地识别 切换和非切换锁存器与下一个最后一个非切换锁存器是故障扫描链中的断点。 这种综合的锁定扰动结合迭代诊断算法用于识别并确定在这种断开的扫描链中的有缺陷的位置。 这种JTAG功能测试功能和最终从其导出的JTAG测试模式可以承载不同的形式和起源，一些产品外部和产品内部。

    Automated System and Processing for Expedient Diagnosis of Broken Shift Registers Latch Chains Using JTAG
    4.
    发明申请
    Automated System and Processing for Expedient Diagnosis of Broken Shift Registers Latch Chains Using JTAG 有权
    自动系统和处理，以便使用JTAG来切换移位寄存器锁存链

    公开(公告)号：US20090210763A1

    公开(公告)日：2009-08-20

    申请号：US12032655

    申请日：2008-02-16

    申请人： Joseph Eckelman ,  Donato O. Forlenza ,  Orazio P. Forlenza ,  Robert B. Gass ,  Phong T. Tran

    发明人： Joseph Eckelman ,  Donato O. Forlenza ,  Orazio P. Forlenza ,  Robert B. Gass ,  Phong T. Tran

    IPC分类号： G01R31/3187 ,  G06F11/00

    CPC分类号： G01R31/318544 ,  G01R31/318536

    摘要： This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.

    摘要翻译： 本发明涉及使用JTAG功能测试模式和执行者来解决在所有锁存系统端口中以串行或侧向宽边插入方式诊断断层扫描链的问题，并且有效地分析响应数据以便容易地识别 切换和非切换锁存器与下一个最后一个非切换锁存器是故障扫描链中的断点。 这种综合的锁定扰动结合迭代诊断算法用于识别并确定在这种断开的扫描链中的有缺陷的位置。 这种JTAG功能测试功能和最终从其导出的JTAG测试模式可以承载不同的形式和起源，一些产品外部和产品内部。

    Self-test for leakage current of driver/receiver stages
    5.
    发明授权
    Self-test for leakage current of driver/receiver stages 失效
    对驱动器/接收器级的漏电流进行自检

    公开(公告)号：US06774656B2

    公开(公告)日：2004-08-10

    申请号：US09682924

    申请日：2001-11-01

    申请人： Ulrich Baur ,  Otto Andreas Torreiter ,  Joseph Eckelman ,  David TinSun Hui

    发明人： Ulrich Baur ,  Otto Andreas Torreiter ,  Joseph Eckelman ,  David TinSun Hui

    IPC分类号： G01R3126

    CPC分类号： G01R31/3004 ,  G01R31/31712

    摘要： The present invention relates to a test for current leakage of driver/receiver stages, and in particular for bi-directional input/output stages (10) of a semiconductor chip. Two dedicated support transistor devices (56, 58) are added into the prior art switching scheme, together with a simple control logic (48, 50, 52, 60, 62, 64) for selectively controlling the two dedicated support transistor devices according to a predetermined test scheme. An on-chip self-test feature provides valid voltage levels which are convertible by the receiver (24) to predictable logic states at the evaluation line RDATA. The test can be performed autonomously on the chip without the requirement for an external test device.

    摘要翻译： 本发明涉及用于驱动器/接收器级的电流泄漏的测试，特别涉及半导体芯片的双向输入/输出级（10）。 两个专用支撑晶体管器件（56,58）与简单的控制逻辑（48,50,52,60,62,64）一起被添加到现有技术的开关方案中，用于根据一个控制逻辑（48,50,52,60,62,64）有选择地控制两个专用支撑晶体管器件 预定的测试方案。 片上自检功能提供有效的电压电平，可由接收器（24）将其转换为评估线RDATA处的可预测逻辑状态。 该测试可以在芯片上自主进行，而不需要外部测试设备。

    Self-test with split, asymmetric controlled driver output stage
    6.
    发明授权
    Self-test with split, asymmetric controlled driver output stage 失效
    自检与分体式，非对称控制驱动器输出级

    公开(公告)号：US06725171B2

    公开(公告)日：2004-04-20

    申请号：US09682925

    申请日：2001-11-01

    申请人： Ulrich Baur ,  Otto Andreas Torreiter ,  Joseph Eckelman ,  David TinSun Hui

    发明人： Ulrich Baur ,  Otto Andreas Torreiter ,  Joseph Eckelman ,  David TinSun Hui

    IPC分类号： G01R3100

    CPC分类号： G01R31/3004

    摘要： The present invention relates to a method and system for full parametric testing of the drive and receive capability of bi-directional driver/receiver-stages, and in particular of bi-directional input/output-stages of a semiconductor chip. Electrical properties, as for example DC-resistance, AC-impedance of a driver stage are tested by at least one test load implemented on the chip itself which causes a characteristic voltage drop usable for test evaluation. Advantageously, the output stage devices of P-type (50, 52) and N-type (54, 56), respectively, are split into at least two sub-devices P1, P2 and N1, N2, and are controlled separately by a control logic (60, 62, 64, 70, 72, 74). Then, for example N2 is used for testing the P device, and P2 is used for testing the N-device. Thus, devices already present on the chip are re-used for test purposes, which makes off-chip testing unnecessary.

    摘要翻译： 本发明涉及用于对双向驱动器/接收机级的驱动和接收能力进行全参数测试的方法和系统，特别是涉及半导体芯片的双向输入/输出级的方法和系统。 通过在芯片本身上实现的至少一个测试负载测试驱动级的电气特性，例如直流电阻，AC阻抗，这导致可用于测试评估的特征电压降。 有利的是，分别将P型（50,52）和N型（54,56）的输出级装置分成至少两个子装置P1，P2和N1，N2，并分别由 控制逻辑（60,62,64,70,72,74）。 然后，例如N2用于测试P设备，P2用于测试N设备。 因此，已经存在于芯片上的器件被重新用于测试目的，这使得不需要芯片外测试。

    Method for at speed testing of multi-clock domain chips
    7.
    发明申请
    Method for at speed testing of multi-clock domain chips 审中-公开
    多时钟域芯片的速度测试方法

    公开(公告)号：US20060195288A1

    公开(公告)日：2006-08-31

    申请号：US11056874

    申请日：2005-02-12

    申请人： Timothy McNamara ,  Joseph Eckelman ,  William Huott

    发明人： Timothy McNamara ,  Joseph Eckelman ,  William Huott

    IPC分类号： G01R27/28

    CPC分类号： G01R31/31727

    摘要： A method of and system for testing multi clock domain devices at functional clock speed by aligning the Launching C2 clocks of the high speed and low speed domains, issuing a Cl->C2 clock in each domain, to at speed test all intra-domain paths and the low speed to high speed paths; aligning the capturing C1 clock edges of the high speed and low speed clocks; and issuing a C2->C1 clock in each domain, to test the high speed to low speed paths.

    摘要翻译： 一种用于通过对齐高速和低速域的启动C2时钟，在每个域中发出Cl-> C2时钟来测试多时钟域设备的方法和系统，以速度测试所有域内路径 和低速到高速路径; 对齐高速和低速时钟的捕获C1时钟边沿; 并在每个域中发出C2-> C1时钟，以测试高速到低速路径。