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13 条记录 (耗时 0.017 秒)

    Self-test for leakage current of driver/receiver stages
    1.
    发明授权
    Self-test for leakage current of driver/receiver stages 失效
    对驱动器/接收器级的漏电流进行自检

    公开(公告)号：US06774656B2

    公开(公告)日：2004-08-10

    申请号：US09682924

    申请日：2001-11-01

    申请人： Ulrich Baur ,  Otto Andreas Torreiter ,  Joseph Eckelman ,  David TinSun Hui

    发明人： Ulrich Baur ,  Otto Andreas Torreiter ,  Joseph Eckelman ,  David TinSun Hui

    IPC分类号： G01R3126

    CPC分类号： G01R31/3004 ,  G01R31/31712

    摘要： The present invention relates to a test for current leakage of driver/receiver stages, and in particular for bi-directional input/output stages (10) of a semiconductor chip. Two dedicated support transistor devices (56, 58) are added into the prior art switching scheme, together with a simple control logic (48, 50, 52, 60, 62, 64) for selectively controlling the two dedicated support transistor devices according to a predetermined test scheme. An on-chip self-test feature provides valid voltage levels which are convertible by the receiver (24) to predictable logic states at the evaluation line RDATA. The test can be performed autonomously on the chip without the requirement for an external test device.

    摘要翻译： 本发明涉及用于驱动器/接收器级的电流泄漏的测试，特别涉及半导体芯片的双向输入/输出级（10）。 两个专用支撑晶体管器件（56,58）与简单的控制逻辑（48,50,52,60,62,64）一起被添加到现有技术的开关方案中，用于根据一个控制逻辑（48,50,52,60,62,64）有选择地控制两个专用支撑晶体管器件 预定的测试方案。 片上自检功能提供有效的电压电平，可由接收器（24）将其转换为评估线RDATA处的可预测逻辑状态。 该测试可以在芯片上自主进行，而不需要外部测试设备。

    Self-test with split, asymmetric controlled driver output stage
    2.
    发明授权
    Self-test with split, asymmetric controlled driver output stage 失效
    自检与分体式，非对称控制驱动器输出级

    公开(公告)号：US06725171B2

    公开(公告)日：2004-04-20

    申请号：US09682925

    申请日：2001-11-01

    申请人： Ulrich Baur ,  Otto Andreas Torreiter ,  Joseph Eckelman ,  David TinSun Hui

    发明人： Ulrich Baur ,  Otto Andreas Torreiter ,  Joseph Eckelman ,  David TinSun Hui

    IPC分类号： G01R3100

    CPC分类号： G01R31/3004

    摘要： The present invention relates to a method and system for full parametric testing of the drive and receive capability of bi-directional driver/receiver-stages, and in particular of bi-directional input/output-stages of a semiconductor chip. Electrical properties, as for example DC-resistance, AC-impedance of a driver stage are tested by at least one test load implemented on the chip itself which causes a characteristic voltage drop usable for test evaluation. Advantageously, the output stage devices of P-type (50, 52) and N-type (54, 56), respectively, are split into at least two sub-devices P1, P2 and N1, N2, and are controlled separately by a control logic (60, 62, 64, 70, 72, 74). Then, for example N2 is used for testing the P device, and P2 is used for testing the N-device. Thus, devices already present on the chip are re-used for test purposes, which makes off-chip testing unnecessary.

    摘要翻译： 本发明涉及用于对双向驱动器/接收机级的驱动和接收能力进行全参数测试的方法和系统，特别是涉及半导体芯片的双向输入/输出级的方法和系统。 通过在芯片本身上实现的至少一个测试负载测试驱动级的电气特性，例如直流电阻，AC阻抗，这导致可用于测试评估的特征电压降。 有利的是，分别将P型（50,52）和N型（54,56）的输出级装置分成至少两个子装置P1，P2和N1，N2，并分别由 控制逻辑（60,62,64,70,72,74）。 然后，例如N2用于测试P设备，P2用于测试N设备。 因此，已经存在于芯片上的器件被重新用于测试目的，这使得不需要芯片外测试。

    Global transition scan based AC method
    4.
    发明授权
    Global transition scan based AC method 失效
    基于全局过渡扫描的AC方法

    公开(公告)号：US06662324B1

    公开(公告)日：2003-12-09

    申请号：US09642371

    申请日：2000-08-21

    申请人： Franco Motika ,  Richard F. Rizzolo ,  Peilin Song ,  William V. Huott ,  Ulrich Baur

    发明人： Franco Motika ,  Richard F. Rizzolo ,  Peilin Song ,  William V. Huott ,  Ulrich Baur

    IPC分类号： G01R3128

    CPC分类号： G01R31/318525 ,  G01R31/31853 ,  G01R31/31858

    摘要： The present invention, enables complementing the state of either the master (L1) or slave latch (L2) in the shift register latches (SRLs) without changing the state of the other. When this is done after properly loading the LSSD scan chain using a normal scan chain sequence, the next system clock sequence can be used to launch a desired transition from each SRL in the scan chain. The actual mechanism for complementing the state of latches in LSSD scan chains can vary depending on which one of the L1 or L2 latch is being complemented; details of the actual scan chain and Shift Register Latch (SRL) design; and the semiconductor chip circuit technology. The complementing function can be provided as an integral part of the SRL design with minimal impact to system path and performance. An alternate complementing method would be to use a self complementing latch function. In this design, the latch to be complemented does not require an additional input containing the complement value, but rather uses its current state as reference and switches to the opposite state. To accomplish this, a complement signal similar to a latch reset (i.e., reset-to-complement) can be used.

    摘要翻译： 本发明能够在不改变另一个状态的情况下补充移位寄存器锁存器（SRL）中的主（L1）或从锁存器（L2）的状态。 当使用正常扫描链序列正确加载LSSD扫描链后，可以使用下一个系统时钟序列来启动扫描链中每个SRL所需的转换。 补充LSSD扫描链中锁存器状态的实际机制可以根据L1或L2锁存器中的哪一个进行补充而变化; 实际扫描链和Shift Register Latch（SRL）设计的细节; 和半导体芯片电路技术。 补充功能可以作为SRL设计的一个组成部分提供，对系统路径和性能影响最小。 一种替代的补充方法是使用自补充锁存功能。 在这种设计中，要补充的锁存器不需要包含补码值的附加输入，而是使用其当前状态作为参考，并切换到相反的状态。 为了实现这一点，可以使用类似于锁存器复位（即，复位到补码）的补码信号。

    Random path delay testing methodology
    5.
    发明授权
    Random path delay testing methodology 有权
    随机路径延迟测试方法

    公开(公告)号：US06728914B2

    公开(公告)日：2004-04-27

    申请号：US09745603

    申请日：2000-12-22

    申请人： Kevin William McCauley ,  William Vincent Huott ,  Mary Prilotski Kusko ,  Peilin Song ,  Richard Frank Rizzolo ,  Ulrich Baur ,  Franco Motika

    发明人： Kevin William McCauley ,  William Vincent Huott ,  Mary Prilotski Kusko ,  Peilin Song ,  Richard Frank Rizzolo ,  Ulrich Baur ,  Franco Motika

    IPC分类号： G01R3128

    CPC分类号： G01R31/318385 ,  G01R31/31858

    摘要： For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated. When all the faults paths of the group falling below the threshold have been tested, a separate determined test generation program is activated. In the generated test, the fault is forced to propagate through the longest path above the threshold value.

    摘要翻译： 对于逻辑电路中的每个逻辑门，确定包含门的所有路径，并且通过其每个输入或启动SRL和每个输出或捕获SRL之间的长度对路径进行分类。 路径被分配单个阈值，然后根据它们相对于阈值的路径长度分类被分成两组，每组中的所有路径被视为单个路径。 然后使用标准LBIST工具模拟伪随机LBIST图案。 当与逻辑门相关联的故障由长度高于阈值的路径的捕获​​SRL检测到时，故障被视为测试并从故障列表中标记出来。 当在低于阈值的任何路径中检测到故障时，它不会被标记，并且故障的测试继续进行，直到测试模式为低于阈值的组的所有路径。 当组件的所有故障路径都低于阈值时，已经测试了单独确定的测试生成程序。 在生成的测试中，故障被迫通过超过阈值的最长路径传播。

    Pressure sensor with pivoting lever
    9.
    发明授权
    Pressure sensor with pivoting lever 失效
    带旋转杆的压力传感器

    公开(公告)号：US06016705A

    公开(公告)日：2000-01-25

    申请号：US87645

    申请日：1998-05-29

    申请人： Ulrich Baur ,  Werner Wallrafen ,  Rudolf Stiller ,  Norbert Schmidt

    发明人： Ulrich Baur ,  Werner Wallrafen ,  Rudolf Stiller ,  Norbert Schmidt

    IPC分类号： G01L9/00 ,  G01L9/02

    CPC分类号： G01L9/0051

    摘要： A pressure sensor has a movable diaphragm stretched directly between the annular pressing surfaces of two housing parts, and an electrical measuring device. In an area that is located radially outward as viewed from the pressing surfaces, the diaphragm has a sealing ring that abuts both housing parts. As a result, transverse vibrations of the diaphragm are reliably supported.

    摘要翻译： 压力传感器具有直接在两个壳体部件的环形压紧表面之间延伸的可移动隔膜和电气测量装置。 在从按压面观察时位于径向外侧的区域中，隔膜具有与两个壳体部分抵接的密封环。 结果，可靠地支撑隔膜的横向振动。

    Integrated circuit arrangement for test inputs
    10.
    发明授权
    Integrated circuit arrangement for test inputs 有权
    用于测试输入的集成电路布置

    公开(公告)号：US08479070B2

    公开(公告)日：2013-07-02

    申请号：US12822287

    申请日：2010-06-24

    申请人： Ulrich Baur ,  Lawrence D. Curley ,  Ronald J. Frishmuth ,  Ralf Ludewig ,  Ching L. Tong ,  Tobias Webel

    发明人： Ulrich Baur ,  Lawrence D. Curley ,  Ronald J. Frishmuth ,  Ralf Ludewig ,  Ching L. Tong ,  Tobias Webel

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31701 ,  G01R31/3172

    摘要： An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.

    摘要翻译： 集成电路芯片包括通信地连接到第一输入/输出（I / O）引脚的主线功能逻辑路径，通信地连接到第一I / O引脚的测试逻辑路径，设置在测试逻辑之间的通信连接之间的锁存器 功能路径和第一I / O引脚，第二I / O引脚通信地连接到锁存器，第二I / O引脚可操作以发送操作以改变锁存器的状态的信号。