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公开(公告)号：US5342805A
公开(公告)日：1994-08-30
申请号：US082951
申请日：1993-07-01
IPC分类号： H01L21/205 , H01L21/20 , H01L21/22 , H01L21/329 , H01L29/165 , H01L29/32
CPC分类号： H01L29/66136 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/0262 , H01L21/221 , H01L29/165 , H01L29/32
摘要： This invention concerns itself with an improved method of producing sharply defined misfit dislocations; (MD) with a new, inexpensive method of doping these misfit dislocations with Au; with invention that a combination of Au and Pt doping in misfit dislocations is superior to any amount of Au and to some specific placements of the misfit dislocations in the device structure.
摘要翻译： 本发明涉及一种改进的产生急剧定义的失配位错的方法; （MD）与一种新的，廉价的方法掺杂这些错配位错与Au; 发明中，在错配位错中Au和Pt掺杂的组合优于任何量的Au以及器件结构中的失配位错的某些特定位置。
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2.发明授权Method of making semiconductor devices using epitaxial techniques to form Si/Si-Ge interfaces and inverting the material 失效使用外延技术制造半导体器件以形成Si / Si-Ge界面并翻转材料的方法
公开(公告)号：US5298457A
公开(公告)日：1994-03-29
申请号：US82952
申请日：1993-07-01
IPC分类号： H01L21/28 , H01L21/20 , H01L21/304 , H01L21/331 , H01L29/161 , H01L29/41 , H01L29/417 , H01L29/73 , H01L21/205
CPC分类号： H01L29/66242 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , Y10S438/928 , Y10S438/938 , Y10S438/977
摘要： The all epitaxial process starts with a high resistivity silicon substrate. Alternating layers of silicon and silicon-germanium are epitaxially grown on the substrate under conditions which create a region with misfit dislocations. A low resistivity silicon layer is then grown over the region. The material is inverted such that the high resistivity layer can be used to form the base of the device. The thickness of the high resistivity layer is adjusted to equal the width of the base of the semiconductor device to be fabricated.
摘要翻译： 所有外延工艺从高电阻率硅衬底开始。 在产生具有失配位错的区域的条件下，在衬底上外延生长硅和硅 - 锗的交替层。 然后在该区域上生长低电阻率硅层。 材料被反转，使得可以使用高电阻率层来形成器件的基极。 将高电阻率层的厚度调整为等于要制造的半导体器件的基极的宽度。
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