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1.发明授权Modulation apparatus/method, demodulation apparatus/method and program presenting medium 有权调制装置/方法，解调装置/方法和程序呈现介质公开(公告)号：US07098819B2
公开(公告)日：2006-08-29
申请号：US10704277
申请日：2003-11-07
申请人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
发明人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
IPC分类号： H03M7/00
CPC分类号： G11B20/1426 , G11B2020/1453 , H03M5/145
摘要： A DSV control bit determining/inserting unit inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit. This modulation unit converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit. The conversion table used by the modulation unit includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remaineder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.
摘要翻译： DSV控制位确定/插入单元将用于执行DSV控制的DSV控制位插入到输入数据串中，并将包括DSV控制位的数据串输出到调制单元。 该调制单元根据转换表将具有2位的基本数据长度的数据串转换为具有3位的基本码长度的可变长度码，并将从转换得到的代码输出到NRZI编码单元。 由调制单元使用的转换表包括用于将最小运行的连续出现次数限制为预定值的替换代码和用于保持游程长度限制的替代代码。 另外，转换表执行转换规则，根据该转换规则，数据字符串中的元素“1”计数的剩余值除以2，值为0或1，总是等于 由数据字符串转换得到的代码中的元素的“1”计数为2。
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2.发明授权Modulation apparatus/method, demodulation apparatus/method and program presenting medium 有权调制装置/方法，解调装置/方法和程序呈现介质公开(公告)号：US06496541B1
公开(公告)日：2002-12-17
申请号：US09320812
申请日：1999-05-27
申请人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
发明人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
IPC分类号： H03M702
CPC分类号： G11B20/1426 , G11B2020/1453 , H03M5/145
摘要： A DSV control bit determining/inserting unit inserts DSV control bits into an input data string and outputs the string including the DSV control bits to a modulation unit which converts the string with basic data length of 2 bits into variable length code with basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit. The conversion table includes substitution codes for limiting the number of consecutive appearances of a minimum run and substitution codes for keeping a run length limit. The conversion table enforces a conversion rule: the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 equals the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.
摘要翻译： DSV控制位确定/插入单元将DSV控制位插入到输入数据串中，并将包括DSV控制位的串输出到调制单元，该调制单元将基本数据长度为2位的字符串转换为基本码长度为 3比特，并将从转换得到的代码输出到NRZI编码单元。 转换表包括用于限制最小运行的连续出现次数的替代代码和用于保持游程长度限制的替代代码。 转换表强制执行转换规则：数据字符串中元素“1”计数的剩余余数除以2，值为0或1等于等于1中元素的“1”计数的余数 由数据字符串转换得到的代码为2。
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3.发明授权Modulation apparatus/method, demodulation apparatus/method and program presenting medium 有权调制装置/方法，解调装置/方法和程序呈现介质公开(公告)号：US07466246B2
公开(公告)日：2008-12-16
申请号：US11556874
申请日：2006-11-06
申请人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
发明人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
IPC分类号： H03M7/00
CPC分类号： G11B20/1426 , G11B2020/1453 , H03M5/145
摘要： A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.
摘要翻译： DSV控制位确定/插入单元11将用于执行DSV控制的DSV控制位插入到输入数据串中，并将包括DSV控制位的数据串输出到调制单元12.调制单元12将数据串以基本 2比特的数据长度根据转换表具有3比特的基本码长度的可变长度码，并将从转换得到的码输出到NRZI编码单元13.调制单元12使用的转换表包括替换码 用于将最小运行的连续出现次数限制为预定值，以及用于保持游程长度限制的替代代码。 另外，转换表强制执行转换规则，根据该转换规则，数据串中的元素的“1”计数的余数除以2，值为0或1，其总和必须等于 由数据字符串转换得到的代码中的元素的“1”计数为2。
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4.发明授权Modulation apparatus/method, demodulation apparatus/method and program presenting medium 有权调制装置/方法，解调装置/方法和程序呈现介质公开(公告)号：US07158060B2
公开(公告)日：2007-01-02
申请号：US11335806
申请日：2006-01-19
申请人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
发明人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
IPC分类号： H03M7/40
CPC分类号： G11B20/1426 , G11B2020/1453 , H03M5/145
摘要： How to record and play back data at a high line density. A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.
摘要翻译： 如何以高线密度记录和播放数据。 DSV控制位确定/插入单元11将用于执行DSV控制的DSV控制位插入到输入数据串中，并将包括DSV控制位的数据串输出到调制单元12。 调制单元12根据转换表将具有2位的基本数据长度的数据串转换为具有3位的基本码长度的可变长度码，并将从转换得到的码输出到NRZI编码单元13。 由调制单元12使用的转换表包括用于将最小运行的连续出现次数限制为预定值的替代代码和用于保持游程长度限制的替代代码。 另外，转换表强制执行转换规则，根据该转换规则，数据串中的元素的“1”计数的余数除以2，值为0或1，其总和必须等于 由数据字符串转换得到的代码中的元素的“1”计数为2。
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5.发明授权Modulation apparatus/method, demodulation apparatus/method and program presenting medium 有权调制装置/方法，解调装置/方法和程序呈现介质公开(公告)号：US06677866B2
公开(公告)日：2004-01-13
申请号：US10263079
申请日：2002-10-02
申请人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
发明人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
IPC分类号： H03M700
CPC分类号： G11B20/1426 , G11B2020/1453 , H03M5/145
摘要： How to record and play back data at a high line density. A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.
摘要翻译： 如何以高线密度记录和播放数据。 DSV控制位确定/插入单元11将用于执行DSV控制的DSV控制位插入到输入数据串中，并将包括DSV控制位的数据串输出到调制单元12.调制单元12将数据串以基本 2比特的数据长度根据转换表具有3比特的基本码长度的可变长度码，并将从转换得到的码输出到NRZI编码单元13.调制单元12使用的转换表包括替换码 用于将最小运行的连续出现次数限制为预定值，以及用于保持游程长度限制的替代代码。 另外，转换表强制执行转换规则，根据该转换规则，数据串中的元素的“1”计数的余数除以2，值为0或1，其总和必须等于 由数据字符串转换得到的代码中的元素的“1”计数为2。
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6.发明授权Device for encoding/decoding n-bit source words into corresponding m-bit channel words, and vice versa 有权将n位源字编码/解码为相应的m位通道字的装置，反之亦然公开(公告)号：US06225921B1
公开(公告)日：2001-05-01
申请号：US09177957
申请日：1998-10-23
申请人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara , Kousuke Nakamura
发明人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara , Kousuke Nakamura
IPC分类号： H03M500
CPC分类号： G11B20/1426 , H03M5/145
摘要： A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C) satisfying a (d,k) constraint, wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (Y1, Y2, Y2). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity preserving (table I). The relations hold that m>n≧1, p≧1, and that p can vary. Preferably, m=n+1. Further, a sync word generator (9) is available for generating a q-bit sync word also satisfying said (d,k) constraint, the said sync word starting with a ‘0’ bit and ending with a ‘0’ bit, the device further comprising merging means (19) for merging said sync word in said stream of databits of the binary channel signal, and that q is an integer value larger than k. (FIG. 1) Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.
摘要翻译： 公开了一种用于将二进制源信号（S）的数据位流编码为满足（d，k）约束的二进制信道信号（C）的数据位流的装置，其中源信号的比特流被分为 n位源字（x1，x2），该装置包括适于将所述源字转换成对应的m位通道字（Y1，Y2，Y2）的转换装置（CM）。 转换装置（CM）还适于将n位源字转换成相应的m位通道字，使得每个n位源字的转换是奇偶校验（表I）。 关系认定m> n> = 1，p> = 1，p可以变化。 优选地，m = n + 1。 此外，同步字生成器（9）可用于生成也满足所述（d，k）约束的q位同步字，所述同步字以“0”位开始并以“0”位结束， 装置还包括用于在所述二进制信道信号的所述数据位流中合并所述同步字，并且所述q是大于k的整数值的合并装置（19）。 （图1）此外，公开了一种解码装置，用于对通过编码装置获得的信道信号进行解码。
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7.发明授权Apparatus for the regeneration of channel-clock information in synchronous data transmission and data-recovery circuit arrangement comprising such apparatus 失效用于再生同步数据传输中的信道时钟信息的装置和包括这种装置的数据恢复电路装置
公开(公告)号：US4807257A
公开(公告)日：1989-02-21
申请号：US895966
申请日：1986-08-12
CPC分类号： H04L7/0334
摘要： A sampled synchronous transmission signal Vt is represented by a series of samples J at equidistant sampling instants. A computing circuit 5 computes the positions R of the sampling instants relative to the rising edges of a virtual reference clock Cref which is phase-locked to the channel clock. For each sampling instant the position R is determined on the basis of the position R of a preceding sampling instant and a measure Q of the difference in time between the sampling interval T and the period L of the virtual reference clock Cref. From the values of the successive samples J an interpolation circuit 2 derives the positions N of the detection-level crossings by the transmission signal Vt, which crossings represent a fixed phase position of the channel clock. After each detection-level crossing the measure Q of the time difference is corrected by circuit 3 and 4, depending on the difference between the positions N and R. A data recovery circuit arrangement recovers the data depending on the values determined for the positions R.
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公开(公告)号：US6157325A
公开(公告)日：2000-12-05
申请号：US307978
申请日：1999-05-10
CPC分类号： H03M5/145
摘要： The invention proposes an apparatus for encoding an information signal. The information signal can be a (d,k) sequence. The apparatus encodes the (d,k) sequence into a (d+n,k+n) sequence by changing the number of zeroes between each time two subsequent ones in the sequence by n. The information signal can also be a RLL sequence of the type (d,k). The apparatus encodes the signal into a RLL sequence of the type (d+n,k+n) by changing the runlengths by n bitcells each.
摘要翻译： 本发明提出一种对信息信号进行编码的装置。 信息信号可以是（d，k）序列。 该装置通过将序列中的每个后续两个之间的零次数改变为n来将（d，k）序列编码为（d + n，k + n）序列。 信息信号也可以是类型（d，k）的RLL序列。 该装置通过将游程长度改变每个n个比特单元，将信号编码为类型（d + n，k + n）的RLL序列。
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9.发明授权Device for encoding/decoding N-bit source words into corresponding M-bit channel words, and vice versa 失效将N位源字编码/解码为相应的M位通道字的装置，反之亦然
公开(公告)号：US5477222A
公开(公告)日：1995-12-19
申请号：US223875
申请日：1994-04-06
CPC分类号： H03M5/145
摘要： A device for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the bitstream of the source signal is divided into n-bit source words (x.sub.1, x.sub.2), which device includes a converting circuit (CM) adapted to convert the source words into corresponding m-bit channel words (y.sub.1, y.sub.2, y.sub.3). The converting circuit (CM) is further adapted to convert n-bit source words into corresponding m-bit words, such that the conversion for each n-bit source word is parity preserving (table I). The relations hold that m>n.gtoreq.1, p.gtoreq.1, and that p can vary. Preferably, m=n+1. Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.
摘要翻译： 一种用于将二进制源信号（S）的数据位流编码成二进制信道信号（C）的数据位流的装置，其中源信号的比特流被划分为n位源字（x1，x2） ，该装置包括适于将源字转换成对应的m位通道字（y1，y2，y3）的转换电路（CM）。 转换电路（CM）还适于将n位源字转换成相应的m位字，使得每个n位源字的转换是奇偶校验（表I）。 关系认为m> n> / = 1，p> / = 1，p可以变化。 优选地，m = n + 1。 此外，公开了一种解码装置，用于对通过编码装置获得的信道信号进行解码。
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公开(公告)号：US4660097A
公开(公告)日：1987-04-21
申请号：US804241
申请日：1985-12-02
CPC分类号： H04N9/8222
摘要： A method of encoding a recording signal which includes a composite color video signal and a digital audio signal, for recording the same on and reading it from an optical video disc is disclosed. The color video signal is frequency-modulated on a carrier wave in the customary manner, while the audio signal pulse-width modulates the carrier wave.
摘要翻译： 公开了一种对包括复合彩色视频信号和数字音频信号的记录信号进行编码的方法，用于将其记录在光学视盘上并将其从光学视盘读取。 彩色视频信号以常规方式在载波上进行频率调制，而音频信号脉宽调制载波。
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