公开(公告)号：US07466246B2

公开(公告)日：2008-12-16

申请号：US11556874

申请日：2006-11-06

申请人： Josephus A. H. M. Kahlman ,  Kornelis A. Schouhamer Immink ,  Gijsbert J. Van Den Enden ,  Toshiyuki Nakagawa ,  Yoshihide Shinpuku ,  Tatsuya Narahara ,  Kosuke Nakamura

发明人： Josephus A. H. M. Kahlman ,  Kornelis A. Schouhamer Immink ,  Gijsbert J. Van Den Enden ,  Toshiyuki Nakagawa ,  Yoshihide Shinpuku ,  Tatsuya Narahara ,  Kosuke Nakamura

IPC分类号： H03M7/00

CPC分类号： G11B20/1426 ,  G11B2020/1453 ,  H03M5/145

摘要： A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.

摘要翻译： DSV控制位确定/插入单元11将用于执行DSV控制的DSV控制位插入到输入数据串中，并将包括DSV控制位的数据串输出到调制单元12.调制单元12将数据串以基本 2比特的数据长度根据转换表具有3比特的基本码长度的可变长度码，并将从转换得到的码输出到NRZI编码单元13.调制单元12使用的转换表包括替换码 用于将最小运行的连续出现次数限制为预定值，以及用于保持游程长度限制的替代代码。 另外，转换表强制执行转换规则，根据该转换规则，数据串中的元素的“1”计数的余数除以2，值为0或1，其总和必须等于 由数据字符串转换得到的代码中的元素的“1”计数为2。

公开(公告)号：US07158060B2

公开(公告)日：2007-01-02

申请号：US11335806

申请日：2006-01-19

申请人： Josephus A. H. M. Kahlman ,  Kornelis A. Schouhamer Immink ,  Gijsbert J. Van Den Enden ,  Toshiyuki Nakagawa ,  Yoshihide Shinpuku ,  Tatsuya Narahara ,  Kosuke Nakamura

发明人： Josephus A. H. M. Kahlman ,  Kornelis A. Schouhamer Immink ,  Gijsbert J. Van Den Enden ,  Toshiyuki Nakagawa ,  Yoshihide Shinpuku ,  Tatsuya Narahara ,  Kosuke Nakamura

IPC分类号： H03M7/40

CPC分类号： G11B20/1426 ,  G11B2020/1453 ,  H03M5/145

摘要： How to record and play back data at a high line density. A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.

摘要翻译： 如何以高线密度记录和播放数据。 DSV控制位确定/插入单元11将用于执行DSV控制的DSV控制位插入到输入数据串中，并将包括DSV控制位的数据串输出到调制单元12。 调制单元12根据转换表将具有2位的基本数据长度的数据串转换为具有3位的基本码长度的可变长度码，并将从转换得到的码输出到NRZI编码单元13。 由调制单元12使用的转换表包括用于将最小运行的连续出现次数限制为预定值的替代代码和用于保持游程长度限制的替代代码。 另外，转换表强制执行转换规则，根据该转换规则，数据串中的元素的“1”计数的余数除以2，值为0或1，其总和必须等于 由数据字符串转换得到的代码中的元素的“1”计数为2。

公开(公告)号：US06496541B1

公开(公告)日：2002-12-17

申请号：US09320812

申请日：1999-05-27

申请人： Josephus A. H. M. Kahlman ,  Kornelis A. Schouhamer Immink ,  Gijsbert J. Van Den Enden ,  Toshiyuki Nakagawa ,  Yoshihide Shinpuku ,  Tatsuya Narahara ,  Kosuke Nakamura

发明人： Josephus A. H. M. Kahlman ,  Kornelis A. Schouhamer Immink ,  Gijsbert J. Van Den Enden ,  Toshiyuki Nakagawa ,  Yoshihide Shinpuku ,  Tatsuya Narahara ,  Kosuke Nakamura

IPC分类号： H03M702

CPC分类号： G11B20/1426 ,  G11B2020/1453 ,  H03M5/145

摘要： A DSV control bit determining/inserting unit inserts DSV control bits into an input data string and outputs the string including the DSV control bits to a modulation unit which converts the string with basic data length of 2 bits into variable length code with basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit. The conversion table includes substitution codes for limiting the number of consecutive appearances of a minimum run and substitution codes for keeping a run length limit. The conversion table enforces a conversion rule: the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 equals the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.

摘要翻译： DSV控制位确定/插入单元将DSV控制位插入到输入数据串中，并将包括DSV控制位的串输出到调制单元，该调制单元将基本数据长度为2位的字符串转换为基本码长度为 3比特，并将从转换得到的代码输出到NRZI编码单元。 转换表包括用于限制最小运行的连续出现次数的替代代码和用于保持游程长度限制的替代代码。 转换表强制执行转换规则：数据字符串中元素“1”计数的剩余余数除以2，值为0或1等于等于1中元素的“1”计数的余数 由数据字符串转换得到的代码为2。

公开(公告)号：US06677866B2

公开(公告)日：2004-01-13

申请号：US10263079

申请日：2002-10-02

申请人： Josephus A. H. M. Kahlman ,  Kornelis A. Schouhamer Immink ,  Gijsbert J. Van Den Enden ,  Toshiyuki Nakagawa ,  Yoshihide Shinpuku ,  Tatsuya Narahara ,  Kosuke Nakamura

发明人： Josephus A. H. M. Kahlman ,  Kornelis A. Schouhamer Immink ,  Gijsbert J. Van Den Enden ,  Toshiyuki Nakagawa ,  Yoshihide Shinpuku ,  Tatsuya Narahara ,  Kosuke Nakamura

IPC分类号： H03M700

CPC分类号： G11B20/1426 ,  G11B2020/1453 ,  H03M5/145

摘要： How to record and play back data at a high line density. A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.

摘要翻译： 如何以高线密度记录和播放数据。 DSV控制位确定/插入单元11将用于执行DSV控制的DSV控制位插入到输入数据串中，并将包括DSV控制位的数据串输出到调制单元12.调制单元12将数据串以基本 2比特的数据长度根据转换表具有3比特的基本码长度的可变长度码，并将从转换得到的码输出到NRZI编码单元13.调制单元12使用的转换表包括替换码 用于将最小运行的连续出现次数限制为预定值，以及用于保持游程长度限制的替代代码。 另外，转换表强制执行转换规则，根据该转换规则，数据串中的元素的“1”计数的余数除以2，值为0或1，其总和必须等于 由数据字符串转换得到的代码中的元素的“1”计数为2。

公开(公告)号：US06225921B1

公开(公告)日：2001-05-01

申请号：US09177957

申请日：1998-10-23

申请人： Josephus A. H. M. Kahlman ,  Kornelis A. Schouhamer Immink ,  Gijsbert J. Van Den Enden ,  Toshiyuki Nakagawa ,  Yoshihide Shimpuku ,  Tatsuya Narahara ,  Kousuke Nakamura

发明人： Josephus A. H. M. Kahlman ,  Kornelis A. Schouhamer Immink ,  Gijsbert J. Van Den Enden ,  Toshiyuki Nakagawa ,  Yoshihide Shimpuku ,  Tatsuya Narahara ,  Kousuke Nakamura

IPC分类号： H03M500

CPC分类号： G11B20/1426 ,  H03M5/145

摘要： A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C) satisfying a (d,k) constraint, wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (Y1, Y2, Y2). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity preserving (table I). The relations hold that m>n≧1, p≧1, and that p can vary. Preferably, m=n+1. Further, a sync word generator (9) is available for generating a q-bit sync word also satisfying said (d,k) constraint, the said sync word starting with a ‘0’ bit and ending with a ‘0’ bit, the device further comprising merging means (19) for merging said sync word in said stream of databits of the binary channel signal, and that q is an integer value larger than k. (FIG. 1) Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

摘要翻译： 公开了一种用于将二进制源信号（S）的数据位流编码为满足（d，k）约束的二进制信道信号（C）的数据位流的装置，其中源信号的比特流被分为 n位源字（x1，x2），该装置包括适于将所述源字转换成对应的m位通道字（Y1，Y2，Y2）的转换装置（CM）。 转换装置（CM）还适于将n位源字转换成相应的m位通道字，使得每个n位源字的转换是奇偶校验（表I）。 关系认定m> n> = 1，p> = 1，p可以变化。 优选地，m = n + 1。 此外，同步字生成器（9）可用于生成也满足所述（d，k）约束的q位同步字，所述同步字以“0”位开始并以“0”位结束， 装置还包括用于在所述二进制信道信号的所述数据位流中合并所述同步字，并且所述q是大于k的整数值的合并装置（19）。 （图1）此外，公开了一种解码装置，用于对通过编码装置获得的信道信号进行解码。

公开(公告)号：US07098819B2

公开(公告)日：2006-08-29

申请号：US10704277

申请日：2003-11-07

申请人： Josephus A. H. M. Kahlman ,  Kornelis A. Schouhamer Immink ,  Gijsbert Van Den Enden ,  Toshiyuki Nakagawa ,  Yoshihide Shinpuku ,  Tatsuya Narahara ,  Kosuke Nakamura

发明人： Josephus A. H. M. Kahlman ,  Kornelis A. Schouhamer Immink ,  Gijsbert Van Den Enden ,  Toshiyuki Nakagawa ,  Yoshihide Shinpuku ,  Tatsuya Narahara ,  Kosuke Nakamura

IPC分类号： H03M7/00

CPC分类号： G11B20/1426 ,  G11B2020/1453 ,  H03M5/145

摘要： A DSV control bit determining/inserting unit inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit. This modulation unit converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit. The conversion table used by the modulation unit includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remaineder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.

摘要翻译： DSV控制位确定/插入单元将用于执行DSV控制的DSV控制位插入到输入数据串中，并将包括DSV控制位的数据串输出到调制单元。 该调制单元根据转换表将具有2位的基本数据长度的数据串转换为具有3位的基本码长度的可变长度码，并将从转换得到的代码输出到NRZI编码单元。 由调制单元使用的转换表包括用于将最小运行的连续出现次数限制为预定值的替换代码和用于保持游程长度限制的替代代码。 另外，转换表执行转换规则，根据该转换规则，数据字符串中的元素“1”计数的剩余值除以2，值为0或1，总是等于 由数据字符串转换得到的代码中的元素的“1”计数为2。

公开(公告)号：US20060132342A1

公开(公告)日：2006-06-22

申请号：US11335806

申请日：2006-01-19

申请人： Josephus Kahlman ,  Kornelis Schouhamer Immink ,  Gijsbert Van Den Enden ,  Toshiyuki Nakagawa ,  Yoshihide Shinpuku ,  Tatsuya Narahara ,  Kosuke Nakamura

发明人： Josephus Kahlman ,  Kornelis Schouhamer Immink ,  Gijsbert Van Den Enden ,  Toshiyuki Nakagawa ,  Yoshihide Shinpuku ,  Tatsuya Narahara ,  Kosuke Nakamura

IPC分类号： H03M3/00

CPC分类号： G11B20/1426 ,  G11B2020/1453 ,  H03M5/145

摘要： How to record and play back data at a high line density. A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.

摘要翻译： 如何以高线密度记录和播放数据。 DSV控制位确定/插入单元11将用于执行DSV控制的DSV控制位插入到输入数据串中，并将包括DSV控制位的数据串输出到调制单元12。 调制单元12根据转换表将具有2位的基本数据长度的数据串转换为具有3位的基本码长度的可变长度码，并将从转换得到的码输出到NRZI编码单元13。 由调制单元12使用的转换表包括用于将最小运行的连续出现次数限制为预定值的替代代码和用于保持游程长度限制的替代代码。 另外，转换表强制执行转换规则，根据该转换规则，数据串中的元素的“1”计数的余数除以2，值为0或1，其总和必须等于 由数据字符串转换得到的代码中的元素的“1”计数为2。

公开(公告)号：US06275175B1

公开(公告)日：2001-08-14

申请号：US09702914

申请日：2000-10-27

申请人： Josephus A. H. M. Kahlman ,  Toshiyuki Nakagawa ,  Yoshihide Shimpuku ,  Tatsuya Narahara ,  Kousuke Nakamura

发明人： Josephus A. H. M. Kahlman ,  Toshiyuki Nakagawa ,  Yoshihide Shimpuku ,  Tatsuya Narahara ,  Kousuke Nakamura

IPC分类号： H03M700

CPC分类号： G11B20/1426 ,  H03M5/145

摘要： A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (y1, y2, y3). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity preserving (table I) (FIG. 1). The relations hold that m>n≧1, p≧1, and that p can vary. Preferably, m=n+1. The device is adapted to convert the 8-bit bit sequence ‘00010001’ in the source signal into the 12-bit bitsequence ‘100010010010’ and to convert the 8-bit bitsequence ‘10010001’ into the 12-bit bitsequence ‘000010010010’, in order to limit the repeated minimum transition runlength in the channel signal. Also other 8-bit sequences require a specific encoding into 12-bit bitsequences in order to limit the k-constraint of the channel signal to 7. Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

摘要翻译： 公开了一种用于将二进制源信号（S）的数据位流编码成二进制信道信号（C）的数据位流的装置，其中源信号的比特流被划分为n位源字（x1， x2），该装置包括适于将所述源字转换成对应的m位通道字（y1，y2，y3）的转换装置（CM）。 转换装置（CM）还适于将n位源字转换成相应的m位通道字，使得每个n位源字的转换是奇偶校验（表1）（图1）。 关系认定m> n> = 1，p> = 1，p可以变化。 优选地，m = n + 1。该装置适于将源信号中的8位比特序列“00010001”转换为12比特比特序列“100010010010”，并将8比特比特序列“10010001”转换为12 比特序列“000010010010”，以便限制信道信号中重复的最小过渡游程长度。 而且其他8位序列还需要对12位比特序列进行特定编码，以将信道信号的k约束限制为7.此外，公开了一种解码装置，用于对通过编码装置获得的信道信号进行解码。

公开(公告)号：US06175318B1

公开(公告)日：2001-01-16

申请号：US09217427

申请日：1998-12-21

申请人： Josephus A. H. M. Kahlman ,  Toshiyuki Nakagawa ,  Yoshihide Shimpuku ,  Tatsuya Narahara ,  Kousuke Nakamura

发明人： Josephus A. H. M. Kahlman ,  Toshiyuki Nakagawa ,  Yoshihide Shimpuku ,  Tatsuya Narahara ,  Kousuke Nakamura

IPC分类号： H03M700

CPC分类号： G11B20/1426 ,  H03M5/145

摘要： An encoder for encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal, the bitstream of the source signal being divided into smaller n-bit source words (x1, x2) which are converted by a logic circuit converter in the encoder into corresponding m-bit channel words, (y1, y2, y3). The conversion of each n-bit source word is parity preserving (see Table I and FIG. 1). The relations hold that m>n≧1, p≧1, and p can vary. Preferably, m=n+1. In order to comply with (d, k) runlength requirements, certain blocks of 2-bit source words are encoded into particular blocks of 3-bit channel words. A decoder is also disclosed for decoding a channel signal produced by the encoder.

摘要翻译： 一种编码器，用于将二进制源信号的数据比特流编码为二进制信道信号的数据比特流，源信号的比特流被分成较小的n比特源字（x1，x2），其被转换为 将编码器中的逻辑电路转换器转换成相应的m位通道字，（y1，y2，y3）。 每个n位源字的转换是奇偶校验（见表1和图1）。 关系认为m> n> = 1，p> = 1，p可以变化。 优选地，m = n + 1。 为了符合（d，k）游程长度要求，2位源字的某些块被编码成3位通道字的特定块。 还公开了一种用于对由编码器产生的信道信号进行解码的解码器。

公开(公告)号：US06313764B1

公开(公告)日：2001-11-06

申请号：US09154528

申请日：1998-09-17

申请人： Toshiyuki Nakagawa ,  Tatsuya Narahara ,  Yoshihide Shinpuku

发明人： Toshiyuki Nakagawa ,  Tatsuya Narahara ,  Yoshihide Shinpuku

IPC分类号： H03M700

CPC分类号： H03M5/145 ,  G11B20/10009 ,  G11B20/1426

摘要： According to the present invention, in the demodulating device, demodulating method and transmitting medium, a channel bit sequence of a variable length code having a minimum run d of 1 or more was decoded to a data sequence, and a code assigned to limit the minimum run d from repeating a predetermined number of times in the channel bit sequence of the variable length code was decoded to a data sequence. Design is therefore easier from the viewpoint of clock reproduction. When all the elements in the table contain a “1” representing an edge, data can be decoded more reliably. Further, when omissions are made in the codes in the table up to d bits from the code sequence lengths of the restriction lengths, data can be decoded more reliably. Thus, a clock is stably reproduced.

摘要翻译： 根据本发明，在解调装置中，解调方法和发送介质中，将具有1或更小的最小游程d的可变长度码的信道比特序列解码为数据序列，并且分配用于限制最小值的码 在可变长度代码的通道位序列中重复预定次数的运行d被解码为数据序列。 因此，从时钟再现的角度来看，设计更容易。 当表中的所有元素包含表示边缘的“1”时，可以更可靠地解码数据。 此外，当从限制长度的代码序列长度到D位中，在表中的代码中省略多达d位时，可以更可靠地解码数据。 因此，稳定地再现时钟。