公开(公告)号：US20100219481A1

公开(公告)日：2010-09-02

申请号：US12684803

申请日：2010-01-08

申请人： Joshua Tseng ,  Yasutoshi Okuno ,  Lars-Ake Ragnarsson ,  Tom Schram ,  Stefan Kubicek ,  Thomas Y. Hoffmann ,  Naohisa Sengoku

发明人： Joshua Tseng ,  Yasutoshi Okuno ,  Lars-Ake Ragnarsson ,  Tom Schram ,  Stefan Kubicek ,  Thomas Y. Hoffmann ,  Naohisa Sengoku

IPC分类号： H01L27/092 ,  H01L21/28

摘要： A method for manufacturing a dual work function device is disclosed. In one aspect, the process includes a first and second region in a substrate. The method includes forming a first transistor in the first region which has a first work function. Subsequently, a second transistor is formed in the second region having a different work function. The process of forming the first transistor includes providing a first gate dielectric stack having a first gate dielectric layer and a first gate dielectric capping layer on the first gate dielectric layer, performing a thermal treatment to modify the first gate dielectric stack, the modified first gate dielectric stack defining the first work function, providing a first metal gate electrode layer on the modified first gate dielectric stack, and patterning the first metal gate electrode layer and the modified first gate dielectric stack.

摘要翻译： 公开了一种用于制造双功能功能装置的方法。 在一个方面，该方法包括在基底中的第一和第二区域。 该方法包括在具有第一功能的第一区域中形成第一晶体管。 随后，在具有不同功函数的第二区域中形成第二晶体管。 形成第一晶体管的过程包括提供在第一栅极介电层上具有第一栅极介电层和第一栅极介电覆盖层的第一栅极电介质堆叠，执行热处理以修改第一栅极电介质堆叠，修改的第一栅极 限定第一功函数的电介质叠层，在修改的第一栅极电介质堆叠上提供第一金属栅极电极层，以及对第一金属栅极电极层和修改的第一栅极电介质堆叠进行构图。

公开(公告)号：US06946305B2

公开(公告)日：2005-09-20

申请号：US10684465

申请日：2003-10-15

申请人： Naohisa Sengoku ,  Michikazu Matsumoto

发明人： Naohisa Sengoku ,  Michikazu Matsumoto

IPC分类号： H01L21/66 ,  H01L23/544 ,  G01R31/26

CPC分类号： H01L22/34

摘要： A wafer for charge amount evaluation having a silicon substrate and p-type regions sandwiched between a first silicon oxide film and a SA-NSG film and surrounded by an undoped silicon film is prepared and subjected to a target process for which an amount of charge is to be evaluated. Then, etching is performed by using a BHF solution. By measuring an amount of etching in the p-type region, an amount of positive charge caused by the process in the wafer can be evaluated quantitatively in an easy and convenient manner.

公开(公告)号：US07851891B2

公开(公告)日：2010-12-14

申请号：US12424894

申请日：2009-04-16

申请人： Naohisa Sengoku ,  Michikazu Matsumoto

发明人： Naohisa Sengoku ,  Michikazu Matsumoto

IPC分类号： H01L29/06

CPC分类号： H01L27/0629

摘要： A method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate; forming an undoped semiconductor film on the first and second insulating films; implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands; forming a third insulating film on the semiconductor regions of the first conductivity type and the undoped semiconductor film; and removing part of the third insulating film by wet etching. At least the second insulating film is formed under the semiconductor regions of the first conductivity type.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一绝缘膜; 去除所述第一绝缘膜的一部分; 在所述半导体衬底上去除了所述第一绝缘膜的所述部分的区域上形成漏电流密度高于所述第一绝缘膜的漏电流密度的第二绝缘膜; 在第一和第二绝缘膜上形成未掺杂的半导体膜; 将杂质注入未掺杂的半导体膜的一部分中，从而限定第一导电类型的半导体区域作为离散岛点缀; 在第一导电类型的半导体区域和未掺杂的半导体膜上形成第三绝缘膜; 并通过湿蚀刻去除第三绝缘膜的一部分。 至少第二绝缘膜形成在第一导电类型的半导体区域下方。

公开(公告)号：US06720241B2

公开(公告)日：2004-04-13

申请号：US10172750

申请日：2002-06-17

申请人： Michikazu Matsumoto ,  Naohisa Sengoku ,  Ayumi Kobayashi

发明人： Michikazu Matsumoto ,  Naohisa Sengoku ,  Ayumi Kobayashi

IPC分类号： H01L21265

CPC分类号： H01L21/823418 ,  H01L21/823437 ,  H01L21/823481

摘要： In a method for manufacturing a semiconductor device, impurity ion is implanted into a semiconductor layer so as to form an ion implantation region in the semiconductor layer, and at least the ion implantation region is turned amorphous. Then, an insulating film is formed on the semiconductor layer at a temperature at which the ion implantation region is not crystallized, and then the semiconductor layer is annealed in a non-oxidizing atmosphere so as to activate the impurity ion implanted into the semiconductor layer.

摘要翻译： 在半导体器件的制造方法中，将杂质离子注入到半导体层中，以在半导体层中形成离子注入区域，并且至少离子注入区域变为无定形。 然后，在离子注入区域未结晶的温度下，在半导体层上形成绝缘膜，然后在非氧化性气氛中对半导体层进行退火，以激活注入到半导体层中的杂质离子。

公开(公告)号：US08004046B2

公开(公告)日：2011-08-23

申请号：US12712688

申请日：2010-02-25

申请人： Naohisa Sengoku

发明人： Naohisa Sengoku

IPC分类号： H01L21/70

CPC分类号： H01L21/823842 ,  H01L21/28052 ,  H01L21/28088 ,  H01L23/485 ,  H01L29/4925 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a gate insulating film formed on a semiconductor substrate, a second gate electrode portion of a gate electrode including a TiN film and a polysilicon film that are successively formed on the gate insulating film, and an interlayer insulating film formed on the semiconductor substrate so as to cover the gate electrode. A contact formed to extend through the interlayer insulating film and the polysilicon film is directly connected to the TiN film.

摘要翻译： 半导体器件具有在半导体衬底上形成的栅极绝缘膜，在栅极绝缘膜上依次形成TiN膜和多晶硅膜的栅电极的第二栅电极部分和形成在半导体上的层间绝缘膜 衬底以覆盖栅电极。 形成为延伸穿过层间绝缘膜和多晶硅膜的触点直接连接到TiN膜。

公开(公告)号：US06509254B1

公开(公告)日：2003-01-21

申请号：US09680053

申请日：2000-10-05

申请人： Michikazu Matsumoto ,  Naohisa Sengoku

发明人： Michikazu Matsumoto ,  Naohisa Sengoku

IPC分类号： H01L213205

CPC分类号： H01L29/4941 ,  H01L21/28061

摘要： After depositing a first metal film of a first metal on a silicon-containing film including silicon as a main component, a second metal film of a nitride of a second metal is deposited on the first metal film. Then, a high-melting-point metal film is deposited on the second metal film, so as to form an electrode structure including the silicon-containing film, the first metal film, the second metal film and the high-melting-point metal film. The electrode structure is then subjected to a heat treatment at 750° C. or more. The first metal film has such a thickness that the first metal is nitrided to be changed into a nitride of the first metal and a silicide layer of the first metal is not formed in a surface portion of the silicon-containing film after the heat treatment.

摘要翻译： 在以包含硅为主要成分的含硅膜上沉积第一金属的第一金属膜之后，在第一金属膜上沉积第二金属的氮化物的第二金属膜。 然后，在第二金属膜上沉积高熔点金属膜，形成包含含硅膜，第一金属膜，第二金属膜和高熔点金属膜的电极结构 。 然后将电极结构在750℃以上进行热处理。 第一金属膜的厚度使得第一金属被氮化以变为第一金属的氮化物，并且在热处理后，在含硅膜的表面部分中不形成第一金属的硅化物层。

公开(公告)号：US06451690B1

公开(公告)日：2002-09-17

申请号：US09679617

申请日：2000-10-05

申请人： Michikazu Matsumoto ,  Naohisa Sengoku

发明人： Michikazu Matsumoto ,  Naohisa Sengoku

IPC分类号： H01L2144

CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/2855

摘要： After forming a barrier film on a silicon-containing film including silicon as a main component, a high-melting-point metal film is deposited on the barrier film, so as to form a laminated structure including the silicon-containing film, the barrier film and the high-melting-point metal film. The laminated structure is subjected to a heat treatment at a temperature of 750° C. or more. The barrier film is formed by forming a first metal film of a nitride of a metal on the silicon-containing film; forming, on the first metal film, a second metal film of the metal or the nitride of the metal with a smaller nitrogen content than the first metal film; and forming, on the second metal film, a third metal film of the nitride of the metal with a larger nitrogen content than the second metal film.

摘要翻译： 在以硅为主要成分的含硅膜上形成阻挡膜之后，在阻挡膜上沉积高熔点金属膜，形成包含含硅膜，阻挡膜 和高熔点金属膜。 层压结构体在750℃以上的温度下进行热处理。 阻挡膜通过在含硅膜上形成金属氮化物的第一金属膜而形成; 在所述第一金属膜上形成所述金属的第二金属膜或所述金属氮化物的氮含量低于所述第一金属膜的金属膜; 以及在所述第二金属膜上形成氮化物的氮化物的第三金属膜与所述第二金属膜相比形成。

公开(公告)号：US20050263833A1

公开(公告)日：2005-12-01

申请号：US11195624

申请日：2005-08-03

申请人： Naohisa Sengoku ,  Michikazu Matsumoto

发明人： Naohisa Sengoku ,  Michikazu Matsumoto

IPC分类号： H01L21/66 ,  H01L23/544 ,  H01L21/336 ,  H01L31/062

CPC分类号： H01L22/34

摘要： A wafer for charge amount evaluation having a silicon substrate and p-type regions sandwiched between a first silicon oxide film and a SA-NSG film and surrounded by an undoped silicon film is prepared and subjected to a target process for which an amount of charge is to be evaluated. Then, etching is performed by using a BHF solution. By measuring an amount of etching in the p-type region, an amount of positive charge caused by the process in the wafer can be evaluated quantitatively in an easy and convenient manner.

摘要翻译： 制备具有硅衬底和夹在第一氧化硅膜和SA-NSG膜之间并被未掺杂硅膜包围的p型区域的电荷量评估用晶片，并进行充电量为 被评估。 然后，使用BHF溶液进行蚀刻。 通过测量p型区域中的蚀刻量，可以以简单方便的方式定量地评估由晶片中的工艺引起的正电荷量。

公开(公告)号：US06879043B2

公开(公告)日：2005-04-12

申请号：US09922804

申请日：2001-08-07

申请人： Michikazu Matsumoto ,  Naohisa Sengoku

发明人： Michikazu Matsumoto ,  Naohisa Sengoku

IPC分类号： C23C14/06 ,  C23C14/34 ,  H01L21/203 ,  H01L21/28 ,  H01L21/285 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L23/48

CPC分类号： H01L21/28061 ,  H01L29/4941

摘要： The electrode structure of this invention includes a silicon-containing film containing silicon as a principal constituent; a barrier metal layer of titanium nitride rich in titanium as compared with a stoichiometric ratio formed on the silicon-containing film; and a metal film with a high melting point formed on the barrier metal layer.

摘要翻译： 本发明的电极结构包括以硅为主要成分的含硅膜; 与形成在含硅膜上的化学计量比相比富含钛的氮化钛阻挡金属层; 和在阻挡金属层上形成的具有高熔点的金属膜。

公开(公告)号：US06593219B2

公开(公告)日：2003-07-15

申请号：US09916447

申请日：2001-07-30

申请人： Michikazu Matsumoto ,  Naohisa Sengoku

发明人： Michikazu Matsumoto ,  Naohisa Sengoku

IPC分类号： H01L213205

CPC分类号： H01L29/6659 ,  C23C26/00 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28247 ,  H01L29/4941

摘要： A first metal film of a first metal is deposited on a silicon-containing film containing silicon as a principal constituent, and a second metal film of a nitride of a second metal is deposited on the first metal film. Thereafter, a metal film with a high melting point is deposited on the second metal film, so as to form a multi-layer film of the silicon-containing film, the first metal film, the second metal film and the metal film with a high melting point. The multi-layer film is then subjected to annealing at a temperature of 750° C. or more. In this case, the first metal is nitrided to be changed into a nitride of the first metal and a silicide layer of the first metal is not formed in a surface portion of the silicon-containing film before the annealing.