公开(公告)号：US06429067B1

公开(公告)日：2002-08-06

申请号：US09765036

申请日：2001-01-17

申请人： Joyce C. Liu ,  James C. Brighten ,  Jeffrey J. Brown ,  John Golz ,  George A. Kaplita ,  Rebecca Mih ,  Senthil Srinivasan ,  Jin Jwang Wu ,  Teresa J. Wu ,  Chienfan Yu

发明人： Joyce C. Liu ,  James C. Brighten ,  Jeffrey J. Brown ,  John Golz ,  George A. Kaplita ,  Rebecca Mih ,  Senthil Srinivasan ,  Jin Jwang Wu ,  Teresa J. Wu ,  Chienfan Yu

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/823842 ,  H01L27/10873

摘要： A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.

摘要翻译： 一种制造双栅结构的方法，包括提供半导体衬底，其具有由栅极氧化层和多晶硅层覆盖的第一器件区域和第二器件区域，在所述多晶硅层上形成第一硬掩模，所述第一硬掩模为 耐受第一蚀刻的材料，但易于在第一硬掩模和多晶硅层上形成第二硬掩模的第二蚀刻，所述第二硬掩模是耐第二蚀刻的材料，但易受第 首先用第一蚀刻蚀刻图案并蚀刻所述第二硬掩模，以在第一器件区域上形成栅极图案，并用第二蚀刻图案化和蚀刻所述第一硬掩模以在第一和第二器件区域上传输栅极图案。

公开(公告)号：US06294449B1

公开(公告)日：2001-09-25

申请号：US09447627

申请日：1999-11-23

申请人： Teresa J. Wu ,  Bomy A. Chen ,  John W. Golz ,  Charles W. Koburger, III ,  Paul C. Parries ,  Christopher J. Waskiewicz ,  Jin Jwang Wu

发明人： Teresa J. Wu ,  Bomy A. Chen ,  John W. Golz ,  Charles W. Koburger, III ,  Paul C. Parries ,  Christopher J. Waskiewicz ,  Jin Jwang Wu

IPC分类号： H01L2144

CPC分类号： H01L21/76897

摘要： A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride cover; the aperture for the bitline contact is time-etched to penetrate only between the gates and not reach the silicon substrate; exposed nitride shoulders of the gate are etched to expose the poly; the remainder of the interlayer dielectric is removed by a selective etch; the exposed poly is re-oxidized to protect the gates; and the aperture bottom is cleaned; so that the thick gate stack of a DRAM is dispensed with in order to improve uniformity of line width across the chip beyond what the DRAM technique can deliver.

摘要翻译： 一对共用共用电极的晶体管 DRAM阵列中的位线具有与位线的自对准接触，其中晶体管栅极堆叠仅具有具有氮化物覆盖层的多晶硅层; 用于位线接触的孔径被时间刻蚀以仅在栅极之间穿透而不到达硅衬底; 蚀刻栅极的暴露的氮化物肩部以暴露多晶硅; 通过选择性蚀刻去除层间电介质的其余部分; 暴露的聚合物被再氧化以保护浇口; 并清洁孔径底部; 从而不需要DRAM的厚栅堆叠，以便提高跨芯片的线宽的均匀性，超出了DRAM技术可以传送的范围。

公开(公告)号：US06303275B1

公开(公告)日：2001-10-16

申请号：US09501653

申请日：2000-02-10

申请人： Robert A. Coles ,  John W. Golz ,  Qinghuang Lin ,  Alan C. Thomas ,  Christopher J. Waskiewicz ,  Teresa J. Wu

发明人： Robert A. Coles ,  John W. Golz ,  Qinghuang Lin ,  Alan C. Thomas ,  Christopher J. Waskiewicz ,  Teresa J. Wu

IPC分类号： G03C500

CPC分类号： G03F7/16 ,  G03F7/168

摘要： A method of forming a resist layer of uniform thickness across a surface patterned with a varying density of high aspect ratio features. A selected material layer having an affinity to a resist coat to be applied over the selected material layer is applied to a wafer having a plurality of recesses before applying a resist coat. After the resist coat is applied over the selected material layer, the selected material diffuses partially into the resist coat to condition a portion of the resist coat to be insoluble in the presence of a developer which is applied after the resist coat. Those portions of the resist coat into which the selected material layer has not diffused then are removed by a developer leaving a uniform resist coat thickness across the wafer.

摘要翻译： 一种形成均匀厚度的抗蚀剂层的方法，该抗蚀剂层跨越具有不同密度的高纵横比特征的图案化的表面。 在施加抗蚀剂涂层之前，将具有与要涂覆在所选择的材料层上的抗蚀剂涂层具有亲和性的所选材料层施加到具有多个凹部的晶片上。 在抗蚀剂涂层施加在所选择的材料层上之后，所选择的材料部分地扩散到抗蚀剂涂层中，以使抗蚀剂涂层的一部分在抗蚀剂涂层之后施加的显影剂的存在下不溶。 所选择的材料层未被扩散的抗蚀剂涂层的那些部分被显影剂除去，在晶片上留下均匀的抗蚀剂涂层厚度。

公开(公告)号：US07111257B2

公开(公告)日：2006-09-19

申请号：US10605169

申请日：2003-09-12

申请人： Norman W. Robson ,  Teresa J. Wu

发明人： Norman W. Robson ,  Teresa J. Wu

IPC分类号： G06F17/50

CPC分类号： G01R31/2884

摘要： A method of using special designed wiring level mask(s) to determine product transistor and circuit performance in a chip during the early portion of the product evaluation cycle saves weeks of time that would have been taken by the passage of the wafer through the fab. The method also saves cost during production by identifying wafers for rework at an early stage.

摘要翻译： 在产品评估周期的早期部分，使用特殊设计的布线电平掩模来确定芯片中的产品晶体管和电路性能的方法节省了通过晶圆通过晶圆所花费的数周时间。 该方法通过在早期阶段识别返工晶片来节省生产成本。