公开(公告)号：US20100038751A1

公开(公告)日：2010-02-18

申请号：US12191430

申请日：2008-08-14

申请人： HUILONG ZHU ,  Babar A. Khan ,  Xi Li ,  Joyce C. Liu ,  Thomas A. Wallner

发明人： HUILONG ZHU ,  Babar A. Khan ,  Xi Li ,  Joyce C. Liu ,  Thomas A. Wallner

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L29/66181 ,  H01L27/10861

摘要： A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it is high enough to ensure that a nitride liner used as a CMP etch stop for STI oxide surrounding a top portion of the poly node will be higher than the STI oxide, so that the nitride liner can be removed prior to forming a silicide contact on top of the poly node.

摘要翻译： 深沟槽（DT）电容器包括硅层中的沟槽，围绕沟槽的掩埋板，衬套沟槽的电介质层和沟槽中的节点导体。 多晶硅节点的顶表面高于硅层的表面，使得其足够高以确保用作CMP蚀刻的氮化物衬垫停止用于围绕多晶硅节点的顶部的STI氧化物将高于 STI氧化物，使得氮化物衬垫可以在在多晶硅节点的顶部形成硅化物接触之前被去除。

公开(公告)号：US20080182372A1

公开(公告)日：2008-07-31

申请号：US11669645

申请日：2007-01-31

申请人： Joyce C. Liu ,  Hongwen Yan ,  Qingyun Yang ,  Ying Zhang

发明人： Joyce C. Liu ,  Hongwen Yan ,  Qingyun Yang ,  Ying Zhang

IPC分类号： H01L21/8238

CPC分类号： H01L29/6653 ,  H01L21/3146 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： A method of forming a complementary metal oxide semiconductor (CMOS) device includes forming an oxide layer on sidewalls and a top surface of a patterned gate conductor, and on sidewalls of a gate insulating layer formed on a semiconductor substrate; forming a first carbon-based layer over the gate conductor, gate insulating layer, and substrate; etching the first carbon-based layer so as to create a first set of carbon spacers; forming a second carbon-based layer over the gate conductor, gate insulating layer, substrate, and first set of carbon spacers; etching the second carbon-based layer so as to create a second set of carbon spacers; forming silicide contacts on the gate conductor, and on source and drain regions formed in the substrate; removing the first and second sets of carbon spacers; and forming a stress-inducing nitride layer over the substrate, silicide contacts, gate conductor, and gate insulating layer.

摘要翻译： 形成互补金属氧化物半导体（CMOS）器件的方法包括在图案化栅极导体的侧壁和顶表面上以及形成在半导体衬底上的栅极绝缘层的侧壁上形成氧化物层; 在栅极导体，栅极绝缘层和衬底上形成第一碳基层; 蚀刻第一碳基层以产生第一组碳间隔物; 在栅极导体，栅极绝缘层，衬底和第一组碳隔离物上形成第二碳基层; 蚀刻第二碳基层以产生第二组碳间隔物; 在栅极导体上形成硅化物触点，以及在衬底中形成的源极和漏极区上; 去除第一和第二组碳间隔物; 以及在衬底上形成应力诱导氮化物层，硅化物接触，栅极导体和栅极绝缘层。

公开(公告)号：US06821890B2

公开(公告)日：2004-11-23

申请号：US09849530

申请日：2001-05-07

申请人： Vincent J. McGahay ,  Thomas H. Ivers ,  Joyce C. Liu ,  Henry A. Nye, III

发明人： Vincent J. McGahay ,  Thomas H. Ivers ,  Joyce C. Liu ,  Henry A. Nye, III

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76879 ,  H01L21/76886 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium nitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.

摘要翻译： 通过提供介入的含锗层，差的粘附层如氮化硅和二氧化硅表现出改善的对铜构件的粘合性。 含锗层是锗锗化锗，氧化锗，氮化锗或其组合。 含锗层增强粘合性，使得不良粘附层不易受到铜构件的分层影响。

公开(公告)号：US06429067B1

公开(公告)日：2002-08-06

申请号：US09765036

申请日：2001-01-17

申请人： Joyce C. Liu ,  James C. Brighten ,  Jeffrey J. Brown ,  John Golz ,  George A. Kaplita ,  Rebecca Mih ,  Senthil Srinivasan ,  Jin Jwang Wu ,  Teresa J. Wu ,  Chienfan Yu

发明人： Joyce C. Liu ,  James C. Brighten ,  Jeffrey J. Brown ,  John Golz ,  George A. Kaplita ,  Rebecca Mih ,  Senthil Srinivasan ,  Jin Jwang Wu ,  Teresa J. Wu ,  Chienfan Yu

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/823842 ,  H01L27/10873

摘要： A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.

摘要翻译： 一种制造双栅结构的方法，包括提供半导体衬底，其具有由栅极氧化层和多晶硅层覆盖的第一器件区域和第二器件区域，在所述多晶硅层上形成第一硬掩模，所述第一硬掩模为 耐受第一蚀刻的材料，但易于在第一硬掩模和多晶硅层上形成第二硬掩模的第二蚀刻，所述第二硬掩模是耐第二蚀刻的材料，但易受第 首先用第一蚀刻蚀刻图案并蚀刻所述第二硬掩模，以在第一器件区域上形成栅极图案，并用第二蚀刻图案化和蚀刻所述第一硬掩模以在第一和第二器件区域上传输栅极图案。

公开(公告)号：US06271595B1

公开(公告)日：2001-08-07

申请号：US09231618

申请日：1999-01-14

申请人： Vincent J. McGahay ,  Thomas H. Ivers ,  Joyce C. Liu ,  Henry A. Nye, III

发明人： Vincent J. McGahay ,  Thomas H. Ivers ,  Joyce C. Liu ,  Henry A. Nye, III

IPC分类号： H01L21328

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76879 ,  H01L21/76886 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium bitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.

摘要翻译： 通过提供介入的含锗层，差的粘附层如氮化硅和二氧化硅表现出改善的对铜构件的粘合性。 含锗层是锗锗，锗，锗或其组合。 含锗层增强粘合性，使得不良粘附层不易受到铜构件的分层影响。

公开(公告)号：US07858485B2

公开(公告)日：2010-12-28

申请号：US12191430

申请日：2008-08-14

申请人： Huilong Zhu ,  Babar A. Khan ,  Xi Li ,  Joyce C. Liu ,  Thomas A. Wallner

发明人： Huilong Zhu ,  Babar A. Khan ,  Xi Li ,  Joyce C. Liu ,  Thomas A. Wallner

IPC分类号： H01L21/20

CPC分类号： H01L29/66181 ,  H01L27/10861

摘要： A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it is high enough to ensure that a nitride liner used as a CMP etch stop for STI oxide surrounding a top portion of the poly node will be higher than the STI oxide, so that the nitride liner can be removed prior to forming a silicide contact on top of the poly node.

摘要翻译： 深沟槽（DT）电容器包括硅层中的沟槽，围绕沟槽的掩埋板，衬套沟槽的电介质层和沟槽中的节点导体。 多晶硅节点的顶表面高于硅层的表面，使得其足够高以确保用作CMP蚀刻的氮化物衬垫停止用于围绕多晶硅节点的顶部的STI氧化物将高于 STI氧化物，使得氮化物衬垫可以在在多晶硅节点的顶部形成硅化物接触之前被去除。

公开(公告)号：US07081393B2

公开(公告)日：2006-07-25

申请号：US10709652

申请日：2004-05-20

申请人： Michael P. Belyansky ,  Joyce C. Liu ,  Hsing Jen Wann ,  Richard Stephen Wise ,  Hongwen Yan

发明人： Michael P. Belyansky ,  Joyce C. Liu ,  Hsing Jen Wann ,  Richard Stephen Wise ,  Hongwen Yan

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An FET transistor has a gate disposed between a source and a drain; a gate dielectric layer disposed underneath the gate; and a spacer on a side of the gate. The gate dielectric layer is conventional oxide and the spacer has a reduced dielectric constant (k). The reduced dielectric constant (k) may be less than 3.85, or it may be less than 7.0 (˜nitride), but greater than 3.85 (˜oxide). Preferably, the spacer comprises a material which can be etched selectively to the gate dielectric layer. The spacer may be porous, and a thin layer is deposited on the porous spacer to prevent moisture absorption. The spacer may comprise a material selected from the group consisting of Black Diamond, Coral, TERA and Blok type materials. Pores may be formed in the spacer material by exposing the spacers to an oxygen plasma.

摘要翻译： FET晶体管具有设置在源极和漏极之间的栅极; 设置在栅极下方的栅介质层; 和在门侧的间隔物。 栅极电介质层是常规的氧化物，间隔物具有降低的介电常数（k）。 降低的介电常数（k）可以小于3.85，或者可以小于7.0（〜氮化物），但大于3.85（〜氧化物）。 优选地，间隔物包括可以选择性地蚀刻到栅极介电层的材料。 间隔物可以是多孔的，并且在多孔间隔物上沉积薄层以防止吸湿。 间隔物可以包括选自黑钻石，珊瑚，TERA和Blok型材料的材料。 可以通过将间隔物暴露于氧等离子体来在间隔物材料中形成孔。

公开(公告)号：US06838347B1

公开(公告)日：2005-01-04

申请号：US10605331

申请日：2003-09-23

申请人： Joyce C. Liu ,  Wesley C. Natzle ,  Richard S. Wise ,  Hongwen Yan ,  Bidan Zhang

发明人： Joyce C. Liu ,  Wesley C. Natzle ,  Richard S. Wise ,  Hongwen Yan ,  Bidan Zhang

IPC分类号： H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L21/32139 ,  H01L21/31116

摘要： A method for reducing line edge roughness (LER) of a semiconductor gate structure includes patterning a photoresist layer formed over an oxide hardmask layer. The photoresist layer is etched so as to transfer a photoresist pattern to the oxide hardmask layer, the photoresist pattern having an initial LER. The exposed surfaces of the oxide hardmask are etched with a chemical oxide removal (COR) so as to form a reaction product on the exposed surfaces, wherein concave portions of the exposed surfaces are etched at a reduced rate with respect to convex portions of the exposed surfaces.

公开(公告)号：US06828187B1

公开(公告)日：2004-12-07

申请号：US10707709

申请日：2004-01-06

申请人： Joyce C. Liu ,  Len Y. Tsou ,  Qingyun Yang

发明人： Joyce C. Liu ,  Len Y. Tsou ,  Qingyun Yang

IPC分类号： H01L218238

CPC分类号： H01L21/823842 ,  H01L21/28035 ,  H01L21/32137

摘要： A method for forming a semiconductor device, includes forming a first locally doped semiconductor region of a first conductivity type and a second locally doped semiconductor region of a second conductivity type over an undoped, lower semiconductor region. A first etch is implemented to simultaneously create a desired pattern in the first and second locally doped semiconductor regions in a manner that also provides a first passivation of exposed sidewalls thereof, wherein the first etch removes material from the first and second locally doped regions at a substantially constant rate with respect to one another, and in a substantially anisotropic manner. A second etch is implemented to complete the desired pattern in the undoped, lower semiconductor region in a manner that protects the first and second locally doped regions from additional material removal therefrom.

摘要翻译： 一种用于形成半导体器件的方法，包括在未掺杂的下半导体区域上形成第一导电类型的第一局部掺杂半导体区域和第二导电类型的第二局部掺杂半导体区域。 实施第一蚀刻以在第一和第二局部掺杂的半导体区域中以提供其暴露的侧壁的第一钝化的方式同时产生期望的图案，其中第一蚀刻从第一和第二局部掺杂区域中去除材料 相对于基本上恒定的速率，并且以基本上各向异性的方式。 实现第二蚀刻以在未掺杂的较低半导体区域中以保护第一和第二局部掺杂区域免除额外材料的方式完成所需图案。

公开(公告)号：US06720249B1

公开(公告)日：2004-04-13

申请号：US09550943

申请日：2000-04-17

申请人： Timothy J. Dalton ,  Christopher V. Jahnes ,  Joyce C. Liu ,  Sampath Purushothaman

发明人： Timothy J. Dalton ,  Christopher V. Jahnes ,  Joyce C. Liu ,  Sampath Purushothaman

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a permanent protective hardmask which protects the dielectric properties of a main dielectric layer having a desirably low dielectric constant in a semiconductor device from undesirable increases in the dielectric constant, undesirable increases in current leakage, and low device yield from surface scratching during subsequent processing steps. The protective hardmask further includes a single layer or dual layer sacrificial hardmask particularly useful when interconnect structures such as via openings and/or lines are formed in the low dielectric material during the course of making the final product. The sacrificial hardmask layers and the permanent hardmask layer may be formed in a single step from a same precursor wherein process conditions are altered to provide films of differing dielectric constants. Most preferably, a dual damascene structure has a tri-layer hardmask comprising silicon carbide BLoK™, PECVD silicon nitride, and PECVD silicon dioxide, respectively, formed over a bulk low dielectric constant interlevel dielectric prior to forming the interconnect structures in the interlevel dielectric.

摘要翻译： 本发明提供一种永久性保护性硬掩模，其保护半导体器件中具有期望的低介电常数的主电介质层的介电性能，不需要介电常数的增加，不期望的电流泄漏增加，以及在表面划伤期间的低的器件产量 后续处理步骤。 保护性硬掩模还包括单层或双层牺牲硬掩模，在制造最终产品的过程中，在低电介质材料中形成诸如通孔开口和/或线之间的互连结构时尤其有用。 牺牲硬掩模层和永久硬掩模层可以从相同的前体在单个步骤中形成，其中改变工艺条件以提供不同介电常数的膜。 最优选地，双镶嵌结构具有三层硬掩模，其在形成层间的互连结构之前分别形成在体低介电常数层间电介质上的碳化硅BLoK TM，PECVD氮化硅和PECVD二氧化硅 电介质。