公开(公告)号：US06429067B1

公开(公告)日：2002-08-06

申请号：US09765036

申请日：2001-01-17

申请人： Joyce C. Liu ,  James C. Brighten ,  Jeffrey J. Brown ,  John Golz ,  George A. Kaplita ,  Rebecca Mih ,  Senthil Srinivasan ,  Jin Jwang Wu ,  Teresa J. Wu ,  Chienfan Yu

发明人： Joyce C. Liu ,  James C. Brighten ,  Jeffrey J. Brown ,  John Golz ,  George A. Kaplita ,  Rebecca Mih ,  Senthil Srinivasan ,  Jin Jwang Wu ,  Teresa J. Wu ,  Chienfan Yu

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/823842 ,  H01L27/10873

摘要： A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.

摘要翻译： 一种制造双栅结构的方法，包括提供半导体衬底，其具有由栅极氧化层和多晶硅层覆盖的第一器件区域和第二器件区域，在所述多晶硅层上形成第一硬掩模，所述第一硬掩模为 耐受第一蚀刻的材料，但易于在第一硬掩模和多晶硅层上形成第二硬掩模的第二蚀刻，所述第二硬掩模是耐第二蚀刻的材料，但易受第 首先用第一蚀刻蚀刻图案并蚀刻所述第二硬掩模，以在第一器件区域上形成栅极图案，并用第二蚀刻图案化和蚀刻所述第一硬掩模以在第一和第二器件区域上传输栅极图案。

公开(公告)号：US20060039226A1

公开(公告)日：2006-02-23

申请号：US11205565

申请日：2005-08-17

申请人： David Hanson ,  Gregory Fredeman ,  John Golz ,  Hoki Kim ,  Paul Parries

发明人： David Hanson ,  Gregory Fredeman ,  John Golz ,  Hoki Kim ,  Paul Parries

IPC分类号： G11C5/14

CPC分类号： G11C5/143 ,  G11C8/08

摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

摘要翻译： 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线 司机。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

公开(公告)号：US06440638B2

公开(公告)日：2002-08-27

申请号：US09161854

申请日：1998-09-28

申请人： John Golz ,  Chorng-Lii Hwang ,  John Zhu

发明人： John Golz ,  Chorng-Lii Hwang ,  John Zhu

IPC分类号： G03C500

CPC分类号： H01L21/31058 ,  G03F7/168 ,  G03F7/2026

摘要： A method for planarizing a layer of photoresist on a substrate. The layer of photoresist is exposed to wavelengths of radiation that the photoresist is sensitive to. The radiation is directed at the layer of photoresist at an oblique angle with respect to a major dimension of the layer of photoresist. The photoresist is developed.

摘要翻译： 用于平坦化基板上的光致抗蚀剂层的方法。 光致抗蚀剂层暴露于光致抗蚀剂敏感的辐射波长。 相对于光致抗蚀剂层的主要尺寸，辐射以相对于光致抗蚀剂层的主要尺寸的倾斜角指向光致抗蚀剂层。 显影光致抗蚀剂。

公开(公告)号：US06954387B2

公开(公告)日：2005-10-11

申请号：US10604375

申请日：2003-07-15

申请人： Hoki Kim ,  Toshiaki Kirihata ,  David R. Hanson ,  Gregory J. Fredeman ,  John Golz

发明人： Hoki Kim ,  Toshiaki Kirihata ,  David R. Hanson ,  Gregory J. Fredeman ,  John Golz

IPC分类号： G11C11/406 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C2207/104

摘要： In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.

摘要翻译： 在包括多个存储体的DRAM中，对于每个存储体，存在分别向上/向下移位的标志位寄存器的一对分离的标志位寄存器。 每个组的比较器提供一个比较器输出。 每个存储体的仲裁器被连接以从该存储体的标志位寄存器和对于该存储体的比较器输出的比较器输出标志位向上信号和标志位降低信号。 仲裁器被连接以接收信号中的冲突并提供冲突信号。 一对标志位寄存器表示每个存储体的刷新状态，并指定准备进行刷新操作的存储体或阵列。

公开(公告)号：US20050013185A1

公开(公告)日：2005-01-20

申请号：US10604375

申请日：2003-07-15

申请人： Hoki Kim ,  Toshiaki Kirihata ,  David Hanson ,  Gregory Fredeman ,  John Golz

发明人： Hoki Kim ,  Toshiaki Kirihata ,  David Hanson ,  Gregory Fredeman ,  John Golz

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C2207/104

摘要： In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.

摘要翻译： 在包括多个存储体的DRAM中，对于每个存储体，存在分别向上/向下移位的标志位寄存器的一对分离的标志位寄存器。 每个组的比较器提供一个比较器输出。 每个存储体的仲裁器被连接以从该存储体的标志位寄存器和对于该存储体的比较器输出的比较器输出标志位向上信号和标志位降低信号。 仲裁器被连接以接收信号中的冲突并提供冲突信号。 一对标志位寄存器表示每个存储体的刷新状态，并指定准备进行刷新操作的存储体或阵列。