公开(公告)号：US20070102734A1

公开(公告)日：2007-05-10

申请号：US11499515

申请日：2006-08-04

申请人： Ju-Ri Kim ,  Jeong-Uk Han ,  Sung-Taeg Kang ,  Chang-Hun Lee ,  Sung-Chul Park

发明人： Ju-Ri Kim ,  Jeong-Uk Han ,  Sung-Taeg Kang ,  Chang-Hun Lee ,  Sung-Chul Park

IPC分类号： H01L29/76

CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11568 ,  H01L29/1041 ,  H01L29/792

摘要： Disclosed is a semiconductor device and method of fabricating the same. The semiconductor device is applicable to various electronic devices such as transistors or memories with transistors. A MOS transistor of the semiconductor device includes a first region and a second region, different in impurity concentration, which are formed in a channel region between source and drain regions. The first region is higher than the second region in impurity concentration. Impurities of the first region are concentrated on a boundary region between an active region and a field isolation film. The first region prevents a punch-through effect in the channel region, while the second region prevents current from decreasing by an increase of impurity during an operation of the transistor. The first region is formed using an additional ion implantation mask, and the second region is formed using an ion implantation mask or formed along with a well.

摘要翻译： 公开了半导体器件及其制造方法。 半导体器件可应用于各种电子器件，例如具有晶体管的晶体管或存储器。 半导体器件的MOS晶体管包括在源极和漏极区域之间的沟道区域中形成的杂质浓度不同的第一区域和第二区域。 第一区域高于杂质浓度的第二区域。 第一区域的杂质集中在活性区域和场隔离膜之间的边界区域上。 第一区域防止沟道区域中的穿通效应，而第二区域在晶体管的操作期间防止电流由杂质增加而减小。 使用另外的离子注入掩模形成第一区域，并且使用离子注入掩模形成第二区域或与阱一起形成。

公开(公告)号：US20070298571A1

公开(公告)日：2007-12-27

申请号：US11896560

申请日：2007-09-04

申请人： Weon-Ho Park ,  Sang-Soo Kim ,  Hyun-Khe Yoo ,  Sung-Chul Park ,  Byoung-Ho Kim ,  Ju-Ri Kim ,  Seung-Beom Yoon ,  Jeong-Uk Han

发明人： Weon-Ho Park ,  Sang-Soo Kim ,  Hyun-Khe Yoo ,  Sung-Chul Park ,  Byoung-Ho Kim ,  Ju-Ri Kim ,  Seung-Beom Yoon ,  Jeong-Uk Han

IPC分类号： H01L21/8247

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/11546

摘要： A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells. A method is described of isolating transistors of a first voltage range from transistors of another voltage range, comprising forming a first well to hold transistors only of a first particular voltage range, and forming a second well to hold transistors only of a second particular voltage range.

摘要翻译： 描述了一种器件，其包括具有第一掺杂剂浓度的第一导电类型的衬底，在衬底中形成的第一阱，在衬底中形成并且比第一阱更深的第一导电类型的第二阱，第二阱具有 比第一掺杂剂浓度高的掺杂剂浓度，以及形成在第二阱上的非易失性存储单元。 描述了一种装置，其包括具有形成在第二阱上的非易失性存储单元的各种导电类型的四个阱。 描述了一种器件，其包括用于隔离多个电压范围的晶体管的多个阱，其中多个阱中的每一个阱包含特定电压范围的至少一个晶体管，并且其中仅一个电压范围的晶体管 在多个孔的每一个内。 描述了一种将第一电压范围的晶体管与另一电压范围的晶体管隔离的方法，包括形成第一阱以仅保持第一特定电压范围的晶体管，以及形成第二阱以仅将晶体管保持在第二特定电压范围 。

公开(公告)号：US07598139B2

公开(公告)日：2009-10-06

申请号：US11896560

申请日：2007-09-04

申请人： Weon-Ho Park ,  Sang-Soo Kim ,  Hyun-Khe Yoo ,  Sung-Chul Park ,  Byoung-Ho Kim ,  Ju-Ri Kim ,  Seung-Beom Yoon ,  Jeong-Uk Han

发明人： Weon-Ho Park ,  Sang-Soo Kim ,  Hyun-Khe Yoo ,  Sung-Chul Park ,  Byoung-Ho Kim ,  Ju-Ri Kim ,  Seung-Beom Yoon ,  Jeong-Uk Han

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/11546

摘要： A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells. A method is described of isolating transistors of a first voltage range from transistors of another voltage range, comprising forming a first well to hold transistors only of a first particular voltage range, and forming a second well to hold transistors only of a second particular voltage range.

摘要翻译： 描述了一种器件，其包括具有第一掺杂剂浓度的第一导电类型的衬底，在衬底中形成的第一阱，在衬底中形成并且比第一阱更深的第一导电类型的第二阱，第二阱具有 比第一掺杂剂浓度高的掺杂剂浓度，以及形成在第二阱上的非易失性存储单元。 描述了一种装置，其包括具有形成在第二阱上的非易失性存储单元的各种导电类型的四个阱。 描述了一种器件，其包括用于隔离多个电压范围的晶体管的多个阱，其中多个阱中的每一个阱包含特定电压范围的至少一个晶体管，并且其中仅一个电压范围的晶体管 在多个孔的每一个内。 描述了一种将第一电压范围的晶体管与另一电压范围的晶体管隔离的方法，包括形成第一阱以仅保持第一特定电压范围的晶体管，以及形成第二阱以仅将晶体管保持在第二特定电压范围 。

公开(公告)号：US07495281B2

公开(公告)日：2009-02-24

申请号：US11488983

申请日：2006-07-19

申请人： Seung-Jin Yang ,  Jeong-Uk Han ,  Kwang-Wook Koh ,  Jae-Hwang Kim ,  Sung-Chul Park ,  Ju-Ri Kim

发明人： Seung-Jin Yang ,  Jeong-Uk Han ,  Kwang-Wook Koh ,  Jae-Hwang Kim ,  Sung-Chul Park ,  Ju-Ri Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/42328 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7883

摘要： In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.

摘要翻译： 在非易失性存储器件及其形成和操作它的方法中，当浮置栅极和控制栅极堆叠时，一个存储器晶体管包括覆盖浮置栅极的两个侧壁的侧壁选择栅极。 侧壁选择门是间隔件形式。 由于侧壁选择栅极在浮动栅极的侧壁上是间隔物形式，所以可以提高电池的集成度。 此外，由于侧壁选择栅极设置在浮置栅极的两个侧壁上，所以可以控制从位线和公共源极线施加的电压，因此可以防止常规的写入/擦除错误。 因此，可以提高阈值电压的分布。

公开(公告)号：US20080316831A1

公开(公告)日：2008-12-25

申请号：US12213278

申请日：2008-06-17

申请人： Sung-Chul Park ,  Jeong-Uk Han ,  Jae-Hwang Kim ,  Ju-Ri Kim

发明人： Sung-Chul Park ,  Jeong-Uk Han ,  Jae-Hwang Kim ,  Ju-Ri Kim

IPC分类号： G11C16/06 ,  G11C11/34 ,  H01L21/336 ,  H01L29/788

CPC分类号： G11C16/0458 ,  G11C8/08 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42332

摘要： A nonvolatile memory device is provided. The nonvolatile memory device includes a semiconductor substrate and memory cell units arranged in a matrix on the semiconductor substrate. Each of the memory cell units includes a tunnel insulation layer on the semiconductor substrate. A first memory gate and a second memory gate are disposed on the tunnel insulation layer. An isolation gate is disposed between the first and second memory gates. A word line covers the first memory gate, the second memory gate and the isolation gate. A method of forming the nonvolatile memory device is also provided.

摘要翻译： 提供非易失性存储器件。 非易失性存储器件包括在半导体衬底上以矩阵布置的半导体衬底和存储单元单元。 每个存储单元单元包括半导体衬底上的隧道绝缘层。 第一存储器栅极和第二存储栅极设置在隧道绝缘层上。 隔离栅极设置在第一和第二存储器栅极之间。 字线覆盖第一存储器栅极，第二存储器栅极和隔离栅极。 还提供了一种形成非易失性存储器件的方法。

公开(公告)号：US07323740B2

公开(公告)日：2008-01-29

申请号：US10870166

申请日：2004-06-18

申请人： Weon-Ho Park ,  Sang-Soo Kim ,  Hyun-Khe Yoo ,  Sung-Chul Park ,  Byoung-Ho Kim ,  Ju-Ri Kim ,  Seung-Beom Yoon ,  Jeong-Uk Han

发明人： Weon-Ho Park ,  Sang-Soo Kim ,  Hyun-Khe Yoo ,  Sung-Chul Park ,  Byoung-Ho Kim ,  Ju-Ri Kim ,  Seung-Beom Yoon ,  Jeong-Uk Han

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/11546

摘要： A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells. A method is described of isolating transistors of a first voltage range from transistors of another voltage range, comprising forming a first well to hold transistors only of a first particular voltage range, and forming a second well to hold transistors only of a second particular voltage range.

摘要翻译： 描述了一种器件，其包括具有第一掺杂剂浓度的第一导电类型的衬底，在衬底中形成的第一阱，在衬底中形成并且比第一阱更深的第一导电类型的第二阱，第二阱具有 比第一掺杂剂浓度高的掺杂剂浓度，以及形成在第二阱上的非易失性存储单元。 描述了一种装置，其包括具有形成在第二阱上的非易失性存储单元的各种导电类型的四个阱。 描述了一种器件，其包括用于隔离多个电压范围的晶体管的多个阱，其中多个阱中的每一个阱包含特定电压范围的至少一个晶体管，并且其中仅一个电压范围的晶体管 在多个孔的每一个内。 描述了一种将第一电压范围的晶体管与另一电压范围的晶体管隔离的方法，包括形成第一阱以仅保持第一特定电压范围的晶体管，以及形成第二阱以仅将晶体管保持在第二特定电压范围 。

公开(公告)号：US20070023820A1

公开(公告)日：2007-02-01

申请号：US11488983

申请日：2006-07-19

申请人： Seung-Jin Yang ,  Jeong-Uk Han ,  Kwang-Wook Koh ,  Jae-Hwang Kim ,  Sung-Chul Park ,  Ju-Ri Kim

发明人： Seung-Jin Yang ,  Jeong-Uk Han ,  Kwang-Wook Koh ,  Jae-Hwang Kim ,  Sung-Chul Park ,  Ju-Ri Kim

IPC分类号： H01L29/788 ,  H01L21/8238

CPC分类号： H01L29/42328 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7883

摘要： In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.

摘要翻译： 在非易失性存储器件及其形成和操作它的方法中，当浮置栅极和控制栅极堆叠时，一个存储器晶体管包括覆盖浮置栅极的两个侧壁的侧壁选择栅极。 侧壁选择门是间隔件形式。 由于侧壁选择栅极在浮动栅极的侧壁上是间隔物形式，所以可以提高电池的集成度。 此外，由于侧壁选择栅极设置在浮置栅极的两个侧壁上，所以可以控制从位线和公共源极线施加的电压，因此可以防止常规的写入/擦除错误。 因此，可以提高阈值电压的分布。

公开(公告)号：US07432159B2

公开(公告)日：2008-10-07

申请号：US11242209

申请日：2005-10-03

申请人： Jae-Hwang Kim ,  Seung-Beom Yoon ,  Kwang-Wook Koh ,  Chang-Hun Lee ,  Sung-Ho Kim ,  Sung-Chul Park ,  Ju-Ri Kim

发明人： Jae-Hwang Kim ,  Seung-Beom Yoon ,  Kwang-Wook Koh ,  Chang-Hun Lee ,  Sung-Ho Kim ,  Sung-Chul Park ,  Ju-Ri Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

摘要翻译： EEPROM器件包括设置在半导体衬底的预定区域以限定有源区的器件隔离层，与器件隔离层交叉的一对控制栅极和有源区，插入控制栅极之间的一对选择栅极， 器件隔离层和有源区以及顺序地堆叠在控制栅极和有源区之间的浮置栅极和隔间栅极电介质图案。EEPROM器件还包括插入浮置栅极和有源区域之间的存储晶体管的栅极绝缘层，以及 隧道绝缘层比存储晶体管的栅极绝缘层薄，并且选择晶体管的栅极绝缘层插入在选择栅极和有源区之间。 隧道绝缘层在与浮动栅极相邻的一侧对准。

公开(公告)号：US20060079045A1

公开(公告)日：2006-04-13

申请号：US11242209

申请日：2005-10-03

申请人： Jae-Hwang Kim ,  Seung-Beom Yoon ,  Kwang-Wook Koh ,  Chang-Hun Lee ,  Sung-Ho Kim ,  Sung-Chul Park ,  Ju-Ri Kim

发明人： Jae-Hwang Kim ,  Seung-Beom Yoon ,  Kwang-Wook Koh ,  Chang-Hun Lee ,  Sung-Ho Kim ,  Sung-Chul Park ,  Ju-Ri Kim

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

公开(公告)号：US07589376B2

公开(公告)日：2009-09-15

申请号：US12199307

申请日：2008-08-27

申请人： Jae-Hwang Kim ,  Seung-Beom Yoon ,  Kwang-Wook Koh ,  Chang-Hun Lee ,  Sung-Ho Kim ,  Sung-Chul Park ,  Ju-Ri Kim

发明人： Jae-Hwang Kim ,  Seung-Beom Yoon ,  Kwang-Wook Koh ,  Chang-Hun Lee ,  Sung-Ho Kim ,  Sung-Chul Park ,  Ju-Ri Kim

IPC分类号： H01L29/94

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

摘要翻译： EEPROM器件包括设置在半导体衬底的预定区域以限定有源区的器件隔离层，与器件隔离层交叉的一对控制栅极和有源区，插入控制栅极之间的一对选择栅极， 器件隔离层和有源区以及顺序地堆叠在控制栅极和有源区之间的浮置栅极和隔间栅极电介质图案。EEPROM器件还包括插入浮置栅极和有源区域之间的存储晶体管的栅极绝缘层，以及 隧道绝缘层比存储晶体管的栅极绝缘层薄，并且选择晶体管的栅极绝缘层插入在选择栅极和有源区之间。 隧道绝缘层在与浮动栅极相邻的一侧对准。