DIGITAL TUNING OF A VOLTAGE CONTROLLED OSCILLATOR OF A PHASE LOCKED LOOP
    1.
    发明申请
    DIGITAL TUNING OF A VOLTAGE CONTROLLED OSCILLATOR OF A PHASE LOCKED LOOP 有权
    相位锁定环的电压控制振荡器的数字调谐

    公开(公告)号:US20060055468A1

    公开(公告)日:2006-03-16

    申请号:US10931050

    申请日:2004-08-30

    IPC分类号: H03L7/00

    CPC分类号: H03L7/087 H03L7/10 H03L7/18

    摘要: This invention describes a method for a component/system level design of an adaptive radio receiver in electronic communication devices (e.g., mobile phones) by providing an automatic digital tuning of a voltage controlled oscillator of a phase locked loop (PLL) instead of a prior-art pre-calibration. A normal PLL for frequency locking is used which does not need any additional pre-calibration blocks to account for different temperatures or any other extreme conditions. If the current switch setting does not allow the locking, i.e., the VCO output signal frequency is still far away from a reference frequency, the PLL “coarse” tuning will cause the switch condition to change and bring the frequency within a reasonable range using an additional phase detector PD2 loop.

    摘要翻译: 本发明通过提供锁相环(PLL)的压控振荡器而不是先前的自动数字调谐来描述用于电子通信设备(例如,移动电话)中的自适应无线电接收机的部件/系统级设计的方法 - 预先校准。 使用用于频率锁定的常规PLL,其不需要任何额外的预校准块来解决不同的温度或任何其它极端条件。 如果当前的开关设置不允许锁定,即VCO输出信号频率仍然远离参考频率,则PLL“粗调”调谐将导致开关条件发生变化,并使频率在合理范围内使用 附加相位检测器PD 2回路。

    Digital tuning of a voltage controlled oscillator of a phase locked loop
    2.
    发明授权
    Digital tuning of a voltage controlled oscillator of a phase locked loop 有权
    锁相环的压控振荡器的数字调谐

    公开(公告)号:US07015763B1

    公开(公告)日:2006-03-21

    申请号:US10931050

    申请日:2004-08-30

    IPC分类号: H03L7/087 H03L7/18

    CPC分类号: H03L7/087 H03L7/10 H03L7/18

    摘要: This invention describes a method for a component/system level design of an adaptive radio receiver in electronic communication devices (e.g., mobile phones) by providing an automatic digital tuning of a voltage controlled oscillator of a phase locked loop (PLL) instead of a prior-art pre-calibration. A normal PLL for frequency locking is used which does not need any additional pre-calibration blocks to account for different temperatures or any other extreme conditions. If the current switch setting does not allow the locking, i.e., the VCO output signal frequency is still far away from a reference frequency, the PLL “coarse” tuning will cause the switch condition to change and bring the frequency within a reasonable range using an additional phase detector PD2 loop.

    摘要翻译: 本发明通过提供锁相环(PLL)的压控振荡器而不是先前的自动数字调谐来描述用于电子通信设备(例如,移动电话)中的自适应无线电接收机的部件/系统级设计的方法 - 预先校准。 使用用于频率锁定的常规PLL,其不需要任何额外的预校准块来解决不同的温度或任何其它极端条件。 如果当前的开关设置不允许锁定,即VCO输出信号频率仍然远离参考频率,则PLL“粗调”调谐将导致开关条件发生变化,并使频率在合理范围内使用 附加相位检测器PD 2回路。

    Reuse of digital-to-analog converters in a multi-mode transmitter
    3.
    发明授权
    Reuse of digital-to-analog converters in a multi-mode transmitter 有权
    数模转换器在多模发射机中的重用

    公开(公告)号:US07403750B2

    公开(公告)日:2008-07-22

    申请号:US11114732

    申请日:2005-04-25

    IPC分类号: H04B1/04

    摘要: A transmitter for generating modulated signals is shown, wherein in a first-type operating mode, a first digital signal is input into a digital-to-analog converter to obtain a first analog signal that is input into a first-type unit, in which a first-type modulated signal is generated in dependence on at least the first analog signal; and wherein in a second-type operating mode, a second digital signal is input into the digital-to-analog converter to obtain a second analog signal that is input into a second-type unit, in which a second-type modulated signal is generated in dependence on at least the second analog signal. Correspondingly, a wireless communication device is shown, as well as a base station, a module in a wireless communication device, a module in a base station, an integrated circuit, a method, a computer program and a computer program product.

    摘要翻译: 示出了用于产生调制信号的发射机,其中在第一类型操作模式中,第一数字信号被输入到数模转换器以获得被输入到第一类型单元中的第一模拟信号,其中 根据至少第一模拟信号产生第一类型调制信号; 并且其中在第二类型操作模式中,第二数字信号被输入到数模转换器中以获得输入到第二类型单元的第二模拟信号,其中产生第二类型调制信号 至少依赖于第二模拟信号。 相应地,示出了无线通信设备,以及基站,无线通信设备中的模块,基站中的模块,集成电路,方法,计算机程序和计算机程序产品。

    Reuse of digital-to-analog converters in a multi-mode transmitter

    公开(公告)号:US20080248766A1

    公开(公告)日:2008-10-09

    申请号:US12157640

    申请日:2008-06-11

    IPC分类号: H04B1/04

    摘要: A transmitter for generating modulated signals is shown, wherein in a first-type operating mode, a first digital signal is input into a digital-to-analog converter to obtain a first analog signal that is input into a first-type unit, in which a first-type modulated signal is generated in dependence on at least the first analog signal; and wherein in a second-type operating mode, a second digital signal is input into the digital-to-analog converter to obtain a second analog signal that is input into a second-type unit, in which a second-type modulated signal is generated in dependence on at least the second analog signal. Correspondingly, a wireless communication device is shown, as well as a base station, a module in a wireless communication device, a module in a base station, an integrated circuit, a method, a computer program and a computer program product.

    Clocking Signal Control
    5.
    发明申请
    Clocking Signal Control 有权
    时钟信号控制

    公开(公告)号:US20110317776A1

    公开(公告)日:2011-12-29

    申请号:US13142772

    申请日:2009-12-22

    IPC分类号: H04L27/04 H04L27/00

    CPC分类号: H04L7/02 G06F1/3203 H04L7/033

    摘要: A system (21) comprises a first circuit (23) for transmitting information to a second circuit (22). The first circuit (23) comprises a signal generator (34) arranged to generate a signal (31) for transmission to the second circuit (22). The signal (31) has a first state for causing the second circuit (22) to perform a first operation and a second state for causing the second circuit (22) to perform a second operation. The signal generator (34) comprises means to modulate the generated signal (31) during a data burst period (52) to encode data into the generated signal (31). The data burst period (52) occurs within a period in which the generated signal (31) is in the second state. The signal (31) is modulated such that the encoded data is distinguishable from the generated signal (31). In an embodiment, a data burst period (52a, 52b) comprises a plurality of data periods (54) during which the state of the signal is representative of the data encoded in the signal (31). The data periods (54) may be separated by padding periods (55) during which the signal (31) is in the second state, The data burst period may be initiated following a delay after the signal changes from being in the first state to being in the second state.

    摘要翻译: 系统(21)包括用于向第二电路(22)发送信息的第一电路(23)。 第一电路(23)包括信号发生器(34),其被布置成产生用于传输到第二电路(22)的信号(31)。 信号(31)具有使第二电路(22)执行第一操作和使第二电路(22)执行第二操作的第二状态的第一状态。 信号发生器(34)包括在数据突发周期(52)期间调制所生成的信号(31)以将数据编码到所生成的信号(31)中的装置。 数据脉冲串周期(52)发生在发生信号(31)处于第二状态的周期内。 调制信号(31)使得编码数据与产生的信号(31)可区分。 在一个实施例中,数据突发时段(52a,52b)包括多个数据周期(54),在此期间信号的状态表示在信号(31)中编码的数据。 数据周期(54)可以由信号(31)处于第二状态的填充周期(55)分开。数据突发周期可以在信号从第一状态变为从第一状态到延迟之后开始 在第二个状态。

    Reuse of digital-to-analog converters in a multi-mode transmitter
    6.
    发明申请
    Reuse of digital-to-analog converters in a multi-mode transmitter 有权
    数模转换器在多模发射机中的重用

    公开(公告)号:US20060240789A1

    公开(公告)日:2006-10-26

    申请号:US11114732

    申请日:2005-04-25

    IPC分类号: H04B1/04

    摘要: A transmitter for generating modulated signals is shown, wherein in a first-type operating mode, a first digital signal is input into a digital-to-analog converter to obtain a first analog signal that is input into a first-type unit, in which a first-type modulated signal is generated in dependence on at least the first analog signal; and wherein in a second-type operating mode, a second digital signal is input into the digital-to-analog converter to obtain a second analog signal that is input into a second-type unit, in which a second-type modulated signal is generated in dependence on at least the second analog signal. Correspondingly, a wireless communication device is shown, as well as a base station, a module in a wireless communication device, a module in a base station, an integrated circuit, a method, a computer program and a computer program product.

    摘要翻译: 示出了用于产生调制信号的发射机,其中在第一类型操作模式中,第一数字信号被输入到数模转换器以获得被输入到第一类型单元中的第一模拟信号,其中 根据至少第一模拟信号产生第一类型调制信号; 并且其中在第二类型操作模式中,第二数字信号被输入到数模转换器中以获得输入到第二类型单元的第二模拟信号,其中产生第二类型调制信号 至少依赖于第二模拟信号。 相应地,示出了无线通信设备,以及基站,无线通信设备中的模块,基站中的模块,集成电路,方法,计算机程序和计算机程序产品。

    Clocking signal control
    7.
    发明授权
    Clocking signal control 有权
    时钟信号控制

    公开(公告)号:US08885734B2

    公开(公告)日:2014-11-11

    申请号:US13142772

    申请日:2009-12-22

    CPC分类号: H04L7/02 G06F1/3203 H04L7/033

    摘要: A system (21) comprises a first circuit (23) for transmitting information to a second circuit (22). The first circuit (23) comprises a signal generator (34) arranged to generate a signal (31) for transmission to the second circuit (22). The signal (31) has a first state for causing the second circuit (22) to perform a first operation and a second state for causing the second circuit (22) to perform a second operation. The signal generator (34) comprises means to modulate the generated signal (31) during a data burst period (52) to encode data into the generated signal (31). The data burst period (52) occurs within a period in which the generated signal (31) is in the second state. The signal (31) is modulated such that the encoded data is distinguishable from the generated signal (31). In an embodiment, a data burst period (52a, 52b) comprises a plurality of data periods (54) during which the state of the signal is representative of the data encoded in the signal (31). The data periods (54) may be separated by padding periods (55) during which the signal (31) is in the second state, The data burst period may be initiated following a delay after the signal changes from being in the first state to being in the second state.

    摘要翻译: 系统(21)包括用于向第二电路(22)发送信息的第一电路(23)。 第一电路(23)包括信号发生器(34),其被布置成产生用于传输到第二电路(22)的信号(31)。 信号(31)具有使第二电路(22)执行第一操作和使第二电路(22)执行第二操作的第二状态的第一状态。 信号发生器(34)包括在数据突发周期(52)期间调制所生成的信号(31)以将数据编码到所生成的信号(31)中的装置。 数据脉冲串周期(52)发生在发生信号(31)处于第二状态的周期内。 调制信号(31)使得编码数据与产生的信号(31)可区分。 在一个实施例中,数据突发时段(52a,52b)包括多个数据周期(54),在此期间信号的状态表示在信号(31)中编码的数据。 数据周期(54)可以由信号(31)处于第二状态的填充周期(55)分开。数据突发周期可以在信号从第一状态变为从第一状态到延迟之后开始 在第二个状态。

    Method and apparatus providing resampling function in a modulus prescaler of a frequency source
    8.
    发明授权
    Method and apparatus providing resampling function in a modulus prescaler of a frequency source 有权
    在频率源的模拟预分频器中提供重采样功能的方法和装置

    公开(公告)号:US06784751B2

    公开(公告)日:2004-08-31

    申请号:US09955874

    申请日:2001-09-18

    IPC分类号: H03L700

    CPC分类号: H03K21/40 H03K21/08 H03L7/193

    摘要: A resampling technique is used to reduce the noise and improve the signal quality in the output of a prescaler circuit (10). The resampling of the output of a last frequency divider stage is accomplished using at least one flip/flop (FF) (e.g., a D-type FF 18) that is clocked by a signal obtained from the input of the prescaler. This reduces or eliminates the noise caused by edge jitter in the output of the prescaler, as well as the effect of spurious signals generated by the prescaler. These teachings can be used in integer N PLLs and in fractional N PLLs, as well as in single and programmable dual or multi-modulus prescalers. Using this technique the current consumption of the prescaler frequency dividers (12, 14, 16) need not be increased in an effort to reduce the prescaler noise, thereby conserving current in battery powered and other applications.

    摘要翻译: 重采样技术用于降低噪声并提高预分频器电路输出中的信号质量(10)。 使用由从预分频器的输入获得的信号计时的至少一个触发器(FF)(例如,D型FF18)来实现最后一个分频器级的输出的重新采样。 这会降低或消除由预分频器的输出引起的边沿抖动引起的噪声,以及由预分频器产生的杂散信号的影响。 这些教导可用于整数N个PLL和分数N个PLL,以及单个和可编程的双模或多模预分频器。 使用这种技术,不需要增加预分频器分频器(12,14,16)的电流消耗,以减少预分频器噪声,从而节省电池供电和其他应用中的电流。