公开(公告)号：US20100276810A1

公开(公告)日：2010-11-04

申请号：US12435306

申请日：2009-05-04

申请人： Jui-Chun Chang ,  Ying-cheng Chen

发明人： Jui-Chun Chang ,  Ying-cheng Chen

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L21/743

摘要： A semiconductor device is provided. A substrate is provided. A buried layer is formed in the substrate. The buried layer comprises an insulating region. A deep trench contact structure is formed in the substrate. The deep trench contact structure comprises a conductive material and a liner layer formed on a side wall of the conductive material. The conductive material is electrically connected with the substrate.

摘要翻译： 提供半导体器件。 提供基板。 在衬底中形成掩埋层。 掩埋层包括绝缘区域。 在衬底中形成深沟槽接触结构。 深沟槽接触结构包括导电材料和形成在导电材料的侧壁上的衬里层。 导电材料与衬底电连接。

公开(公告)号：US08921202B2

公开(公告)日：2014-12-30

申请号：US12986225

申请日：2011-01-07

申请人： Geeng-Lih Lin ,  Kwang-Ming Lin ,  Shang-Hui Tu ,  Jui-Chun Chang

发明人： Geeng-Lih Lin ,  Kwang-Ming Lin ,  Shang-Hui Tu ,  Jui-Chun Chang

IPC分类号： H01L21/76 ,  H01L21/74 ,  H01L21/8249 ,  H01L27/06

CPC分类号： H01L29/417 ,  H01L21/743 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0684

摘要： The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer.

摘要翻译： 本发明提供一种半导体器件。 在衬底中形成掩埋层。 在衬底中形成第一深沟槽接触结构。 第一深沟槽接触结构包括导体和形成在导体的侧壁上的衬里层。 第一深沟槽接触结构的底表面与埋层接触。

公开(公告)号：USD926589S1

公开(公告)日：2021-08-03

申请号：US29716803

申请日：2019-12-12

申请人： Jui-Chun Chang

设计人： Jui-Chun Chang

公开(公告)号：US20200268111A1

公开(公告)日：2020-08-27

申请号：US16568800

申请日：2019-09-12

申请人： Jui-Chun Chang

发明人： Jui-Chun Chang

IPC分类号： A43D3/08

摘要： An inflatable shoe stretcher includes a bag body that is formed by coupling outer peripheries of two bag sheets and that defines an air-filling space therein, an one-way air inflow unit that is mounted between the bag sheets for filling air into the air-filling space, and a heat-sealed unit that is formed by coupling portions of the bag sheets. The heat-sealed unit includes two main heat-sealed subunits for segregating the air-filling space into three air-filling space portions. The bag body is able to be bent alongside the main heat-sealed subunits when the air-filling space portions are filled with air.

公开(公告)号：US20120001225A1

公开(公告)日：2012-01-05

申请号：US13232975

申请日：2011-09-14

申请人： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

发明人： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

IPC分类号： H01L29/739

CPC分类号： H01L29/7393 ,  H01L27/0259

摘要： Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

摘要翻译： 介绍了绝缘栅双极晶体管（IGBT）静电放电（ESD）保护装置。 IGBT-ESD器件包括半导体衬底和设置在半导体衬底上的图案化绝缘区域，其限定第一有源区域和第二有源区域。 在半导体衬底的第一有源区中形成高V N阱。 在半导体衬底的第二有源区中形成P体掺杂区域，其中高V N阱和P体掺杂区域以暴露半导体衬底的预定距离被分离。 P +掺杂漏区设置在高V N阱中。 P +扩散区域和N +掺杂源极区域设置在P体掺杂区域中。 栅极结构设置在半导体衬底上，其一端与N +掺杂源极区相邻，另一端延伸在绝缘区上。

公开(公告)号：US20100087054A1

公开(公告)日：2010-04-08

申请号：US12323411

申请日：2008-11-25

申请人： Shanghui L. Tu ,  Hung-Shern Tsai ,  Jui-Chun Chang

发明人： Shanghui L. Tu ,  Hung-Shern Tsai ,  Jui-Chun Chang

IPC分类号： H01L21/22

CPC分类号： H01L21/2652 ,  H01L21/02532 ,  H01L21/2253 ,  H01L29/0847 ,  H01L29/66659

摘要： The invention provides a method for forming a deep well region of a power device, including: providing a substrate with a first sacrificial layer thereon; forming a first patterned mask layer on the first sacrificial layer exposing a first open region; performing a first doping process to the first open region to form a first sub-doped region; removing the first patterned mask layer and the first sacrificial layer; forming an epitaxial layer on the substrate; forming a second sacrificial layer on the epitaxial layer; forming a second patterned mask layer on the second sacrificial layer exposing a second open region; performing a second doping process to the second open region to form a second sub-doped region; removing the second patterned mask layer; performing an annealing process to make the first and the second sub-doped regions form a deep well region; and removing the second sacrificial layer.

摘要翻译： 本发明提供一种用于形成功率器件的深阱区域的方法，包括：在其上提供衬底上的第一牺牲层; 在所述第一牺牲层上形成暴露第一开放区域的第一图案化掩模层; 对所述第一开放区域执行第一掺杂工艺以形成第一子掺杂区域; 去除所述第一图案化掩模层和所述第一牺牲层; 在衬底上形成外延层; 在所述外延层上形成第二牺牲层; 在所述第二牺牲层上形成暴露第二开放区域的第二图案化掩模层; 对所述第二开放区域执行第二掺杂工艺以形成第二子掺杂区域; 去除所述第二图案化掩模层; 执行退火处理以使第一和第二子掺杂区域形成深阱区域; 并移除第二牺牲层。

公开(公告)号：US08907382B2

公开(公告)日：2014-12-09

申请号：US12266509

申请日：2008-11-06

申请人： Jui-Chun Chang

发明人： Jui-Chun Chang

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L21/762 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/76264 ,  H01L27/0922 ,  H01L29/7824

摘要： A semiconductor device is provided. An insulating buried layer is formed in a substrate. Deep trench insulating structures are formed on the insulating buried layer. A deep trench contact structure is formed between the deep trench insulating structures. The deep trench contact structure is electrically connected with the substrate under the insulating buried layer.

摘要翻译： 提供半导体器件。 在衬底中形成绝缘掩埋层。 在绝缘埋层上形成深沟槽绝缘结构。 在深沟槽绝缘结构之间形成深沟槽接触结构。 深沟槽接触结构在绝缘掩埋层下与衬底电连接。

公开(公告)号：US20130092955A1

公开(公告)日：2013-04-18

申请号：US13403734

申请日：2012-02-23

申请人： Shin-Jia Chiou ,  Chung Hsin Lin ,  Chi-Lung Wu ,  Jui-Chun Chang

发明人： Shin-Jia Chiou ,  Chung Hsin Lin ,  Chi-Lung Wu ,  Jui-Chun Chang

IPC分类号： H01L33/06 ,  H01L33/32 ,  H01L33/34 ,  H01L33/10

CPC分类号： H01L33/405 ,  H01L33/0079 ,  H01L33/32 ,  H01L33/40

摘要： A light-emitting diode (LED) and fabricating method thereof. The method includes: providing a first substrate and forming an epitaxial portion on the first substrate; forming at least one reflection layer on the epitaxial portion; forming a metal barrier portion on the reflection layer; etching the epitaxial portion and the barrier portion by a first etching process, so as to form a plurality of epitaxial layers and a plurality of metal barrier layers, an etch channel is formed between adjacent epitaxial layers, and each metal barrier layer enwraps a corresponding reflection layer and covers all of a surface of a corresponding epitaxial layer; forming a first bonding layer on the metal barrier layer; and forming a second substrate on the first bonding layer and removing the first substrate.

摘要翻译： 发光二极管（LED）及其制造方法。 该方法包括：提供第一衬底并在第一衬底上形成外延部分; 在所述外延部分上形成至少一个反射层; 在反射层上形成金属阻挡部分; 通过第一蚀刻工艺蚀刻外延部分和势垒部分，以便形成多个外延层和多个金属阻挡层，在相邻的外延层之间形成蚀刻通道，并且每个金属阻挡层包含相应的反射 并覆盖相应外延层的所有表面; 在所述金属阻挡层上形成第一结合层; 以及在所述第一接合层上形成第二衬底并移除所述第一衬底。

公开(公告)号：US08049307B2

公开(公告)日：2011-11-01

申请号：US12358943

申请日：2009-01-23

申请人： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

发明人： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

IPC分类号： H01L29/93

CPC分类号： H01L29/7393 ,  H01L27/0259

摘要： Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

摘要翻译： 介绍了绝缘栅双极晶体管（IGBT）静电放电（ESD）保护装置。 IGBT-ESD器件包括半导体衬底和设置在半导体衬底上的图案化绝缘区域，其限定第一有源区域和第二有源区域。 在半导体衬底的第一有源区中形成高V N阱。 在半导体衬底的第二有源区中形成P体掺杂区域，其中高V N阱和P体掺杂区域以暴露半导体衬底的预定距离被分离。 P +掺杂漏区设置在高V N阱中。 P +扩散区域和N +掺杂源极区域设置在P体掺杂区域中。 栅极结构设置在半导体衬底上，其一端与N +掺杂源极区相邻，另一端延伸在绝缘区上。

公开(公告)号：US20100187566A1

公开(公告)日：2010-07-29

申请号：US12358943

申请日：2009-01-23

申请人： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

发明人： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

IPC分类号： H01L29/739

CPC分类号： H01L29/7393 ,  H01L27/0259

摘要： Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

摘要翻译： 介绍了绝缘栅双极晶体管（IGBT）静电放电（ESD）保护装置。 IGBT-ESD器件包括半导体衬底和设置在半导体衬底上的图案化绝缘区域，其限定第一有源区域和第二有源区域。 在半导体衬底的第一有源区中形成高V N阱。 在半导体衬底的第二有源区中形成P体掺杂区域，其中高V N阱和P体掺杂区域以暴露半导体衬底的预定距离被分离。 P +掺杂漏区设置在高V N阱中。 P +扩散区域和N +掺杂源极区域设置在P体掺杂区域中。 栅极结构设置在半导体衬底上，其一端与N +掺杂源极区相邻，另一端延伸在绝缘区上。