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公开(公告)号：US5302952A
公开(公告)日：1994-04-12
申请号：US936492
申请日：1992-08-28
申请人： Jules D. Campbell, Jr. , Carl D. Wiseman , William D. Huston , Colleen M. Collins , Mark R. Heene
发明人： Jules D. Campbell, Jr. , Carl D. Wiseman , William D. Huston , Colleen M. Collins , Mark R. Heene
CPC分类号： G06F3/05
摘要： An analog-to-digital conversion module, QADC (1), and method minimize software involvement by providing a pause capacility. Each queue in the QADC (1) has one or more Conversion Command Words, CCWs (82), in a Conversion Command Word Table (62). Each conversion command word, CCW (82), has a Pause bit which can be used to create multiple sub-queues of A/D conversions without requiring the use of interrupts. The Pause bit can be used to place a queue in a pause state. When a queue enters a pause state, the scanning of CCWs (82) is stopped. The queue must then receive a trigger in order for the scanning of CCWs (82) to continue again.
摘要翻译： 模数转换模块QADC（1）和方法通过提供暂停能力来最大限度地减少软件参与。 在转换命令字表（62）中，QADC（1）中的每个队列具有一个或多个转换命令字CCW（82）。 每个转换命令字CCW（82）都有一个暂停位，可以用于创建多个A / D转换子队列，而不需要使用中断。 暂停位可用于将队列置于暂停状态。 当队列进入暂停状态时，CCW（82）的扫描被停止。 队列必须接收一个触发器才能扫描CCW（82）再次继续。
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2.发明授权
公开(公告)号：US5168276A
公开(公告)日：1992-12-01
申请号：US852830
申请日：1992-03-16
摘要： An analog-to-digital conversion module and method minimize software involvement by providing a programmable control table comprising a plurality of conversion command words (CCW's). Each CCW designates conversion parameters such as channel and reference selection, input sample time, and re-sample inhibit for one conversion operation, upon conclusion of which a digital value is stored in a corresponding result table. A set of CCW's defines one or more conversion sequences. Upon conclusion of each sequence, an interrupt can be issued and the result table may be read by an associated device, such as a CPU. If desired, the CCW sequence may be dynamically altered during operation of the conversion system.
摘要翻译： 模数转换模块和方法通过提供包括多个转换命令字（CCW's）的可编程控制表来最小化软件参与。 当结束数字值存储在相应的结果表中时，每个CCW指定转换参数，例如通道和参考选择，输入采样时间和重新采样禁止。 一组CCW定义了一个或多个转换序列。 在每个序列的结论之后，可以发出一个中断，并且结果表可以由诸如CPU的相关设备读取。 如果需要，可以在转换系统的操作期间动态地改变CCW序列。
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公开(公告)号：US5081454A
公开(公告)日：1992-01-14
申请号：US577222
申请日：1990-09-04
CPC分类号： H03M1/1245 , G06F3/05 , H03M1/1225
摘要： An analog-to-digital conversion system module and method provides programmable times for sampling analog input signals. Software involvement is minimized by providing a command word which includes information specifying a sample time. The command word may be stored in a register or memory table. The command word or words may specify the conversion time per analog input channel or group of channels, and per conversion or conversion sequence. In one embodiment a control table comprises a plurality of conversion command words (CCW's). Each CCW designates conversion parameters including the input sample time.
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4.发明授权
公开(公告)号：US4816996A
公开(公告)日：1989-03-28
申请号：US77578
申请日：1987-07-24
申请人： Susan C. Hill , Joseph Jelemensky , Mark R. Heene
发明人： Susan C. Hill , Joseph Jelemensky , Mark R. Heene
CPC分类号： H04L7/0008 , G06F13/4291
摘要： A serial peripheral interface achieves compatibility with devices having previous such interfaces while significantly reducing the amount of intervention required on the part of the controlling data processing device. Many serial transfers are written to a memory by the controlling device together with command and control information. The interface then executes the stored, or queued, transfers autonomously. Features such as programmable transfer length, programmable chip selects, an alterable queue pointer, and others contribute to the flexibility and usefulness of the interface.
摘要翻译： 串行外围接口实现与具有先前这样的接口的设备的兼容性，同时显着减少了控制数据处理设备部分所需的干预量。 许多串行传输由控制设备连同命令和控制信息一起写入存储器。 接口然后自动执行存储或排队的传输。 诸如可编程传输长度，可编程芯片选择，可更改的队列指针等功能有助于界面的灵活性和有用性。
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5.发明授权
公开(公告)号：US4958277A
公开(公告)日：1990-09-18
申请号：US342651
申请日：1989-04-21
IPC分类号： G06F13/42
CPC分类号： G06F13/423
摘要： A serial peripheral interface achieves compatibility with devices having previous such interfaces while singificantly reducing the amount of intervention required on the part of the controlling data processing device. Many serial transfers are written to a memory by the controlling device together with command and control information. The interface then executes the stored, or queued, transfers autonomously. Features such as programmable transfer length, programmable chip selects, an alterable queue pointer, and others contribute to the flexibility and usefulness of the interface.
摘要翻译： 串行外围接口实现与具有先前这样的接口的设备的兼容性，同时显着地减少了控制数据处理设备的部分所需的干预量。 许多串行传输由控制设备连同命令和控制信息一起写入存储器。 接口然后自动执行存储或排队的传输。 诸如可编程传输长度，可编程芯片选择，可更改的队列指针等功能有助于界面的灵活性和有用性。
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6.发明授权Circuitry for automatically entering and terminating an initialization mode in a data processing system in response to a control signal 失效用于响应于控制信号在数据处理系统中自动进入和终止初始化模式的电路
公开(公告)号：US5263168A
公开(公告)日：1993-11-16
申请号：US709552
申请日：1991-06-03
CPC分类号： G06F9/4403 , G06F12/0638
摘要： A data processing system (10), comprised of a central processing unit (14) and a memory system (16), has an efficient initialization operation. The memory system (16) provides a bus interface unit (20) to automatically determine whether the system (10) should execute an initialization operation or function in a normal mode of operation. The memory system (16) begins execution of the initialization operation of the system (10) in response to both a logic value of a reset signal and a value of an address transferred by an address bus. The memory system (16) automatically terminates execution of the initialization operation in response to the value of the address transferred by the address bus.
摘要翻译： 由中央处理单元（14）和存储器系统（16）组成的数据处理系统（10）具有有效的初始化操作。 存储器系统（16）提供总线接口单元（20），以自动确定系统（10）是否应该在正常操作模式下执行初始化操作或功能。 存储器系统（16）响应于复位信号的逻辑值和由地址总线传送的地址的值两者开始执行系统（10）的初始化操作。 存储器系统（16）响应于由地址总线传送的地址的值自动终止初始化操作的执行。
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公开(公告)号：US5138709A
公开(公告)日：1992-08-11
申请号：US508214
申请日：1990-04-11
CPC分类号： G06F11/0745 , G06F11/0751
摘要： In a microprocessor system including arbitration for an interrupt, an apparatus and method for monitoring the arbitration lines to determine whether an interrupt request is real or spurious is includued. Once an interrupt acknowledge signal is provided, the interrupting apparatus must arbitrate for the interrupt slot. If no arbitration occurs the interrupt request was spurious and bus error is activated.
摘要翻译： 在包括用于中断的仲裁的微处理器系统中，包括用于监视仲裁线以确定中断请求是真实还是假的中断的装置和方法。 一旦中断确认信号被提供，中断装置必须仲裁中断插槽。 如果没有发生仲裁，则中断请求是虚假的，总线错误被激活。
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8.发明授权Single chip microcomputer with patching and configuration controlled by on-board non-volatile memory 失效单片机具有由板载非易失性存储器控制的修补和配置
公开(公告)号：US4802119A
公开(公告)日：1989-01-31
申请号：US026511
申请日：1987-03-17
CPC分类号： G06F9/328 , G06F15/7814 , G06F8/66
摘要： A single chip microcomputer with patching and configuration is provided with blocks of patch memory which may be patched over faulty and/or obsolete areas of the microcomputer's memory map under control of starting address registers which are implemented in on-board non-volatile memory. The starting address registers, and enable registers which control whether each patch block is placed in the memory map, are programmable under control of the microcomputer's CPU. Newly programmed values in these registers are not effective to alter the memory map until a reset sequence enables a latch. In particular embodiments, patch blocks may overlie mask ROM, internal EPROM and/or EEPROM, external memory or devices or any other desireable portion of the memory map.
摘要翻译： 具有修补和配置的单片微计算机具有块补丁存储器块，其可以在实现在板载非易失性存储器中的起始地址寄存器的控制下在微机存储器映射的故障和/或过时区域进行修补。 启动地址寄存器和控制每个补丁块是否置于存储器映射中的使能寄存器都可以在微机CPU的控制下进行编程。 这些寄存器中的新编程值在重置序列启用锁存器之前，无法更改存储器映射。 在特定实施例中，贴片块可以覆盖掩模ROM，内部EPROM和/或EEPROM，外部存储器或设备或存储器映射的任何其它可望的部分。
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