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公开(公告)号：US20120062313A1
公开(公告)日：2012-03-15
申请号：US13232529
申请日：2011-09-14
IPC分类号： G05F3/02
CPC分类号： G05F3/205 , H03K19/0013
摘要： A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.
摘要翻译： MOS功率晶体管的衬底的动态偏置电路可以包括第一开关，其被配置为当晶体管的栅极电压使晶体管导通时，将衬底连接到电流源，该电流源向前偏置晶体管的本征源极 - 衬底二极管 。 电流源可以包括与衬底和电源电压之间的本征二极管相同的导通方向的二极管堆叠。
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公开(公告)号：US08570096B2
公开(公告)日：2013-10-29
申请号：US13232529
申请日：2011-09-14
IPC分类号： G05F1/10
CPC分类号： G05F3/205 , H03K19/0013
摘要： A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.
摘要翻译： MOS功率晶体管的衬底的动态偏置电路可以包括第一开关，其被配置为当晶体管的栅极电压使晶体管导通时，将衬底连接到电流源，该电流源向前偏置晶体管的本征源极 - 衬底二极管 。 电流源可以包括与衬底和电源电压之间的本征二极管相同的导通方向的二极管堆叠。
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3.发明授权公开(公告)号：US07538599B2
公开(公告)日：2009-05-26
申请号：US11939946
申请日：2007-11-14
申请人： Alexandre Valentian
发明人： Alexandre Valentian
IPC分类号： G05F1/10
CPC分类号： H03K17/687 , H03K17/162 , H03K19/0016 , H03K2217/0036
摘要： The invention relates to electronic integrated circuits capable of operating either in active mode or in standby mode and to have, in standby mode, a very low current consumption. According to the invention, the leakage current of a power transistor inserted in series between a supply terminal and an active circuit is controlled by a gate reverse overbias in the following manner: a first reference transistor, and a second reference transistor identical to the first, are biased with the same gate reverse overbias voltage as the power transistor, the first transistor having its source linked to the supply terminal, and the second reference transistor having its source linked to its drain. The leakage currents in these two transistors are compared, and it is considered that the optimal bias of the gate is obtained when the leakage currents are equal. Applications to circuits supplied by a battery or a cell (portable telephones, cameras, portable computers, etc.).
摘要翻译： 本发明涉及能够以活动模式或待机模式操作并且在待机模式下具有非常低的电流消耗的电子集成电路。 根据本发明，串联插在电源端子和有源电路之间的功率晶体管的漏电流以下列方式由栅极反向栅极控制：与第一参考晶体管相同的第一参考晶体管和第二参考晶体管， 被偏置与功率晶体管相同的门反向过电压，第一晶体管的源极与供电端连接，第二参考晶体管的源极与其漏极相连。 比较这两个晶体管中的漏电流，并且认为当泄漏电流相等时获得栅极的最佳偏置。 适用于由电池或电池（便携式电话，相机，便携式计算机等）提供的电路。
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4.发明授权Integrated circuit with a power transistor gate bias controlled by the leakage current 有权具有功率晶体管栅极偏置的集成电路由漏电流控制公开(公告)号：US07928797B2
公开(公告)日：2011-04-19
申请号：US12608616
申请日：2009-10-29
CPC分类号： H03K19/0013 , H03K17/063 , H03K19/00384
摘要： The invention relates to electronic integrated circuits capable of operating either in active mode or in standby mode and of having, in standby mode, a very low current consumption. According to the invention, the leakage current of a power transistor inserted in series between a supply terminal and an active circuit is controlled by a gate reverse overbias in the following manner: a voltage step-up charge pump generates a gate bias voltage from pulses delivered by an oscillator having its frequency controlled by a current. The control current Ic is the leakage current of a transistor having technological characteristics similar to those of the power transistor. The system optimizes the current consumption in standby mode, the frequency of the oscillator being reduced when the gate is biased so as to minimize the leakage current. The invention is applicable to circuits powered by a battery or a cell (mobile telephones, cameras, portable computers, etc.).
摘要翻译： 本发明涉及能够以活动模式或待机模式操作并且在待机模式下具有非常低的电流消耗的电子集成电路。 根据本发明，串联插入在电源端子和有源电路之间的功率晶体管的漏电流由栅极反向过电流以下列方式控制：升压电荷泵由输出的脉冲产生栅极偏置电压 通过其频率由电流控制的振荡器。 控制电流Ic是具有与功率晶体管类似的技术特性的晶体管的漏电流。 该系统优化待机模式下的电流消耗，当栅极偏置时，振荡器的频率降低，从而最小化漏电流。 本发明适用于由电池或电池（移动电话，照相机，便携式计算机等）供电的电路。
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5.发明申请Integrated Circuit with a Power Transistor Gate Bias Controlled by the Leakage Current 有权具有由漏电流控制的功率晶体管栅极偏置的集成电路公开(公告)号：US20100117720A1
公开(公告)日：2010-05-13
申请号：US12608616
申请日：2009-10-29
IPC分类号： G05F1/10
CPC分类号： H03K19/0013 , H03K17/063 , H03K19/00384
摘要： The invention relates to electronic integrated circuits capable of operating either in active mode or in standby mode and of having, in standby mode, a very low current consumption. According to the invention, the leakage current of a power transistor inserted in series between a supply terminal and an active circuit is controlled by a gate reverse overbias in the following manner: a voltage step-up charge pump generates a gate bias voltage from pulses delivered by an oscillator having its frequency controlled by a current. The control current Ic is the leakage current of a transistor having technological characteristics similar to those of the power transistor. The system optimizes the current consumption in standby mode, the frequency of the oscillator being reduced when the gate is biased so as to minimize the leakage current. The invention is applicable to circuits powered by a battery or a cell (mobile telephones, cameras, portable computers, etc.).
摘要翻译： 本发明涉及能够以活动模式或待机模式操作并且在待机模式下具有非常低的电流消耗的电子集成电路。 根据本发明，串联插入在电源端子和有源电路之间的功率晶体管的漏电流由栅极反向过电流以下列方式控制：升压电荷泵由输出的脉冲产生栅极偏置电压 通过其频率由电流控制的振荡器。 控制电流Ic是具有与功率晶体管类似的技术特性的晶体管的漏电流。 该系统优化待机模式下的电流消耗，当栅极偏置时，振荡器的频率降低，从而最小化漏电流。 本发明适用于由电池或电池（移动电话，照相机，便携式计算机等）供电的电路。
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6.发明授权公开(公告)号：US07683653B2
公开(公告)日：2010-03-23
申请号：US12024518
申请日：2008-02-01
申请人： Alexandre Valentian
发明人： Alexandre Valentian
IPC分类号： H03K19/00
CPC分类号： G01R31/2642
摘要： The invention concerns a process and a circuit designed to improve the life duration of electronic field-effect integrated circuit transistors and in particular those with a thin film gate dielectric. According to the invention, an aging measurement tS is supplied by measuring the charge or discharge time at a reference voltage VREF of the gate of a field effect transistor T1, previously pre-charged to a predefined test voltage VP, and brought to high impedance. Depending on the aging measurement obtained, the operational voltage measurement conditions of the transistor can be maintained or modified to reduce the stress applied to the dielectric.
摘要翻译： 本发明涉及一种设计用于改善电子场效应集成电路晶体管的寿命的工艺和电路，特别是具有薄膜栅极电介质的电路。 根据本发明，通过在先前预充电到预定的测试电压VP的场效应晶体管T1的栅极的参考电压VREF下测量充电或放电时间来提供老化测量tS，并使其成为高阻抗。 取决于所获得的老化测量值，可以维持或修改晶体管的工作电压测量条件以减小施加于电介质的应力。
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