公开(公告)号：US07928797B2

公开(公告)日：2011-04-19

申请号：US12608616

申请日：2009-10-29

申请人： Alexandre Valentian ,  Olivier Thomas

发明人： Alexandre Valentian ,  Olivier Thomas

IPC分类号： G05F3/02 ,  G05F1/10

CPC分类号： H03K19/0013 ,  H03K17/063 ,  H03K19/00384

摘要： The invention relates to electronic integrated circuits capable of operating either in active mode or in standby mode and of having, in standby mode, a very low current consumption. According to the invention, the leakage current of a power transistor inserted in series between a supply terminal and an active circuit is controlled by a gate reverse overbias in the following manner: a voltage step-up charge pump generates a gate bias voltage from pulses delivered by an oscillator having its frequency controlled by a current. The control current Ic is the leakage current of a transistor having technological characteristics similar to those of the power transistor. The system optimizes the current consumption in standby mode, the frequency of the oscillator being reduced when the gate is biased so as to minimize the leakage current. The invention is applicable to circuits powered by a battery or a cell (mobile telephones, cameras, portable computers, etc.).

摘要翻译： 本发明涉及能够以活动模式或待机模式操作并且在待机模式下具有非常低的电流消耗的电子集成电路。 根据本发明，串联插入在电源端子和有源电路之间的功率晶体管的漏电流由栅极反向过电流以下列方式控制：升压电荷泵由输出的脉冲产生栅极偏置电压 通过其频率由电流控制的振荡器。 控制电流Ic是具有与功率晶体管类似的技术特性的晶体管的漏电流。 该系统优化待机模式下的电流消耗，当栅极偏置时，振荡器的频率降低，从而最小化漏电流。 本发明适用于由电池或电池（移动电话，照相机，便携式计算机等）供电的电路。

公开(公告)号：US20100117720A1

公开(公告)日：2010-05-13

申请号：US12608616

申请日：2009-10-29

申请人： Alexandre Valentian ,  Olivier Thomas

发明人： Alexandre Valentian ,  Olivier Thomas

IPC分类号： G05F1/10

CPC分类号： H03K19/0013 ,  H03K17/063 ,  H03K19/00384

摘要： The invention relates to electronic integrated circuits capable of operating either in active mode or in standby mode and of having, in standby mode, a very low current consumption. According to the invention, the leakage current of a power transistor inserted in series between a supply terminal and an active circuit is controlled by a gate reverse overbias in the following manner: a voltage step-up charge pump generates a gate bias voltage from pulses delivered by an oscillator having its frequency controlled by a current. The control current Ic is the leakage current of a transistor having technological characteristics similar to those of the power transistor. The system optimizes the current consumption in standby mode, the frequency of the oscillator being reduced when the gate is biased so as to minimize the leakage current. The invention is applicable to circuits powered by a battery or a cell (mobile telephones, cameras, portable computers, etc.).

摘要翻译： 本发明涉及能够以活动模式或待机模式操作并且在待机模式下具有非常低的电流消耗的电子集成电路。 根据本发明，串联插入在电源端子和有源电路之间的功率晶体管的漏电流由栅极反向过电流以下列方式控制：升压电荷泵由输出的脉冲产生栅极偏置电压 通过其频率由电流控制的振荡器。 控制电流Ic是具有与功率晶体管类似的技术特性的晶体管的漏电流。 该系统优化待机模式下的电流消耗，当栅极偏置时，振荡器的频率降低，从而最小化漏电流。 本发明适用于由电池或电池（移动电话，照相机，便携式计算机等）供电的电路。

公开(公告)号：US08232168B2

公开(公告)日：2012-07-31

申请号：US12521311

申请日：2007-12-28

申请人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

发明人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

IPC分类号： H01L21/336

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L29/78645

摘要： A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of said double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block.

摘要翻译： 一种用于制造具有一个或多个双栅极晶体管的微电子器件的方法，包括：a）在至少包括构成为形成双栅极晶体管的第一栅极的第一块的至少一个衬底上形成一个或多个结构，并且至少 第二块，其被配置为形成所述双栅极的第二栅极，所述第一块和所述第二块位于至少一个半导体区的相对侧上，并且通过第一栅极介电区和第二栅极电介质与所述半导体区分离 并且b）使用相对于第一块选择性的至少一种植入，在所述结构中掺杂至少一个给定结构的第二块中的至少一个或多个半导体区域，所述第二块被硬掩模覆盖， 硬掩模的临界尺寸大于第二块的临界尺寸。

公开(公告)号：US20120126333A1

公开(公告)日：2012-05-24

申请号：US13262376

申请日：2010-04-01

申请人： Olivier Thomas ,  Jean-Philippe Noel

发明人： Olivier Thomas ,  Jean-Philippe Noel

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203

摘要： The invention relates to an integrated circuit including an active semiconducting layer separated from a semiconducting substrate layer by an embedded insulating material surface, including: first and second transistors (205, 213) of a single type; first and second floorplans arranged vertically perpendicular to the first and second transistors; wherein the first transistor has a doping of the floorplan thereof, opposite that of the source thereof, and a first threshold voltage; the second transistor has a doping of the floorplan thereof, identical to that of the source thereof, and a second threshold voltage; the first threshold voltage is dependent on the potential difference applied between the source and the floorplan of the first transistor; and the second threshold voltage is dependent on the potential difference applied between the source and the floorplan of the second transistor.

摘要翻译： 本发明涉及一种集成电路，其包括通过嵌入式绝缘材料表面与半导体衬底层分离的有源半导体层，其包括：单一类型的第一和第二晶体管（205,213）; 垂直于第一和第二晶体管垂直排列的第一和第二平面图; 其中所述第一晶体管具有与其源极相反的其平面图的掺杂和第一阈值电压; 第二晶体管具有与其源极相同的其平面图的掺杂和第二阈值电压; 第一阈值电压取决于施加在第一晶体管的源极和平面布置图之间的电位差; 并且第二阈值电压取决于施加在第二晶体管的源极和平面布置图之间的电位差。

公开(公告)号：US20100264496A1

公开(公告)日：2010-10-21

申请号：US12740907

申请日：2008-11-07

申请人： Olivier Thomas ,  Thomas Ernst

发明人： Olivier Thomas ,  Thomas Ernst

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/78696

摘要： A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k≧1) parallel in a direction forming a non-zero angle with the main plane of the substrate, and one or more second transistor(s), respectively including a number m of channels, such that m>k, parallel in a direction forming a non-zero angle, or an orthogonal direction, with the main plane of the substrate.

摘要翻译： 一种微电子器件，在衬底上包括诸如SRAM存储单元的至少一个元件; 分别包括在与衬底的主平面形成非零角度的方向上平行的k个通道（k≥1）和一个或多个第二晶体管的一个或多个第一晶体管 包括数个m个通道，使得与形成非零角度的方向或正交方向平行的m> k与衬底的主平面。

公开(公告)号：US07812410B2

公开(公告)日：2010-10-12

申请号：US12168417

申请日：2008-07-07

申请人： Michael Collonge ,  Maud Vinet ,  Olivier Thomas

发明人： Michael Collonge ,  Maud Vinet ,  Olivier Thomas

IPC分类号： H01L27/20 ,  H01L41/04 ,  H01L41/083

CPC分类号： G11C23/00 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/515 ,  H01L29/78654

摘要： A microelectronic device, including at least one transistor including: on a substrate, a semiconductor zone with a channel zone covered with a gate dielectric zone, a mobile gate, suspended above the gate dielectric zone and separated from the gate dielectric zone by an empty space, which the gate is located at an adjustable distance from the gate dielectric zone, and a piezoelectric actuation device including a stack formed by at least one layer of piezoelectric material resting on a first biasing electrode, and a second biasing electrode resting on the piezoelectric material layer, wherein the gate is attached to the first biasing electrode and is in contact with the first biasing electrode, and the piezoelectric actuation device is configured to move the gate with respect to the channel zone.

摘要翻译： 一种微电子器件，包括至少一个晶体管，其包括：在衬底上，具有覆盖有栅极介电区的沟道区的半导体区，悬浮在栅极介电区上方的移动栅极，并与栅极介电区隔开空位 栅极位于与栅极介电区域可调节的距离处，以及压电致动装置，其包括由至少一层静电在第一偏置电极上的压电材料形成的叠层，以及沉积在压电材料上的第二偏置电极 层，其中所述栅极附接到所述第一偏置电极并且与所述第一偏置电极接触，并且所述压电致动装置被配置为相对于所述沟道区移动所述栅极。

公开(公告)号：US09093499B2

公开(公告)日：2015-07-28

申请号：US13627059

申请日：2012-09-26

申请人： Jean-Philippe Noel ,  Bastien Giraud ,  Olivier Thomas

发明人： Jean-Philippe Noel ,  Bastien Giraud ,  Olivier Thomas

IPC分类号： H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L21/84 ,  H01L27/12 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/768 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0928 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78648

摘要： A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.

摘要翻译： 一种制造方法包括：IC，其包括半导体衬底，掩埋绝缘层和半导体层的堆叠;形成在半导体层中和/或上的半导体层的第一电子部件;产生第一偏置电压的偏置电路;第一和第二 偏置电路施加与第一偏置电压相同的偏置电压的通孔型互连，将第一电子部件与第一和第二互连分开的第一绝缘沟槽，具有第一类型的掺杂的第一接地平面 在第一电子部件的埋置绝缘层铅垂之下，并且在第一绝缘沟槽下方延伸并且与第一互连接触，并且具有与第一类型相反的第二类型掺杂的第一阱具有第一接地层 并且在第一绝缘沟槽下方延伸并与第二互连接触。

公开(公告)号：US08674443B2

公开(公告)日：2014-03-18

申请号：US13164164

申请日：2011-06-20

申请人： Philippe Coronel ,  Claire Fenouillet-Beranger ,  Stephane Denorme ,  Olivier Thomas

发明人： Philippe Coronel ,  Claire Fenouillet-Beranger ,  Stephane Denorme ,  Olivier Thomas

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L21/76283 ,  H01L29/78645

摘要： A support substrate comprises first and second counter-electrodes arranged in the same plane at the level of a surface of the support substrate. An electrically insulating area separates the first and second counter-electrodes. A semi-conducting area with first and second portions is separated from the support substrate by an electrically insulating material. The electrically insulating material is different from the material forming the support substrate. The first portion of the semi-conducting area is facing the first counter-electrode. The second portion of the semi-conducting area is facing the second counter-electrode.

摘要翻译： 支撑基板包括在支撑基板的表面的高度处布置在同一平面中的第一和第二对置电极。 电绝缘区域分离第一和第二对置电极。 具有第一和第二部分的半导体区域通过电绝缘材料与支撑衬底分离。 电绝缘材料与形成支撑基板的材料不同。 半导电区域的第一部分面向第一对置电极。 半导体区域的第二部分面向第二对置电极。

公开(公告)号：US08320198B2

公开(公告)日：2012-11-27

申请号：US12866821

申请日：2009-02-16

申请人： Olivier Thomas ,  Bastien Giraud

发明人： Olivier Thomas ,  Bastien Giraud

IPC分类号： G11C7/00

CPC分类号： G11C11/412

摘要： A random access memory cell including: two double-gate access transistors respectively arranged between a first bit line and a first storage node and between a second bit line and a second storage node, a word line, a first double-gate load transistor and a second double-gate load transistor, a first double-gate driver transistor and a second double-gate driver transistor, a mechanism to apply a given potential to at least one electrode of each of the load or driver transistors, and a mechanism to cause the given potential to vary.

摘要翻译： 一种随机存取存储单元，包括：分别布置在第一位线和第一存储节点之间以及第二位线和第二存储节点之间的两个双栅极存取晶体管，字线，第一双栅极负载晶体管和 第二双栅极负载晶体管，第一双栅极驱动晶体管和第二双栅极驱动晶体管，将给定电位施加到每个负载或驱动晶体管的至少一个电极的机构，以及使得 给予潜力有所不同。

公开(公告)号：US08105906B2

公开(公告)日：2012-01-31

申请号：US12521377

申请日：2007-12-28

申请人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

发明人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

IPC分类号： H01L21/336

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L29/78645

摘要： A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block.

摘要翻译： 一种用于制造具有一个或多个非对称双栅极晶体管的微电子器件的方法，包括：a）在至少包括形成双栅晶体管的第一栅极的第一半导体块的衬底上形成一个或多个结构，以及 至少第二半导体块，其被配置为形成所述双栅极晶体管的第二栅极，所述第一块和所述第二块位于至少一个半导体区的相对侧上，并且通过第一栅极介电区与所述半导体区分离;以及 分别为第二栅极介电区，以及b）使用相对于第一块选择性的至少一种注入，在结构中的至少一个给定结构的第二块中至少掺杂一个或多个半导体区域。