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公开(公告)号：US5383080A
公开(公告)日：1995-01-17
申请号：US917995
申请日：1992-07-24
申请人： Jun Etoh , Masakazu Aoki , Masashi Horiguchi , Shigeki Ueda , Hitoshi Tanaka , Kazuhiko Kajigaya , Tsugio Takahashi , Hiroshi Kawamoto
发明人： Jun Etoh , Masakazu Aoki , Masashi Horiguchi , Shigeki Ueda , Hitoshi Tanaka , Kazuhiko Kajigaya , Tsugio Takahashi , Hiroshi Kawamoto
IPC分类号： G11C11/407 , G05F1/46 , G11C5/14 , G11C11/401 , H01L21/822 , H01L21/8242 , H01L27/02 , H01L27/04 , H01L27/10 , H01L27/108 , H03G11/00 , H02H3/00
CPC分类号： G11C5/147 , G05F1/465 , H01L27/0248 , H01L2224/48091
摘要： A voltage limiter circuit is disposed in a semiconductor IC chip in order to reduce an operating voltage of an internal circuit of a scaled-down element. A small capacitance of a Vcc wiring by the disposition constitutes a resonance circuit together with an inductance of the Vcc wiring. Resonance at the resonance circuit causes large variation of a supply current and noise. An additional capacitance is connected between the Vcc wiring and a Vss wiring in order to suppress the variation and noise. The capacitance is formed by a PN junction and is connected in series to a damping resistance.
摘要翻译： 为了降低按比例缩小的元件的内部电路的工作电压，在半导体IC芯片中设置限压电路。 通过配置的Vcc布线的小电容与Vcc布线的电感一起构成谐振电路。 谐振电路的共振引起电源电流和噪声的大幅变化。 Vcc接线和Vss接线之间连接一个额外的电容，以抑制变化和噪音。 电容由PN结形成，并串联连接到阻尼电阻。
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公开(公告)号：US07292496B2
公开(公告)日：2007-11-06
申请号：US11472252
申请日：2006-06-22
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
摘要翻译： 本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。 半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。 在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。
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公开(公告)号：US06934210B2
公开(公告)日：2005-08-23
申请号：US10190480
申请日：2002-07-09
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C11/409 , G11C29/08 , G11C7/00 , G11C7/04
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
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公开(公告)号：US06851017B2
公开(公告)日：2005-02-01
申请号：US10174962
申请日：2002-06-20
申请人： Masashi Horiguchi , Shigeki Ueda , Hideharu Yahata
发明人： Masashi Horiguchi , Shigeki Ueda , Hideharu Yahata
IPC分类号： G11C11/403 , G11C11/401 , G11C11/406 , G11C29/00 , G11C29/04 , H01L27/10 , G06F12/00
CPC分类号： G11C29/783 , G11C11/406
摘要： The present invention provides a semiconductor memory capable of shortening a refresh cycle time and reducing power consumption at refresh. The semiconductor memory includes an address input circuit for generating each of internal address signals, a redundant judgement circuit for receiving the internal address signal therein and determining whether the corresponding address corresponds to an address for a defective word line of a plurality of normal word lines, and an address counter for generating refresh address signals for sequentially refreshing the plurality of normal word lines and redundant word lines. The redundant judgment circuit is deactivated upon refresh.
摘要翻译： 本发明提供了能够缩短刷新周期时间并降低刷新时的功耗的半导体存储器。 半导体存储器包括用于产生每个内部地址信号的地址输入电路，用于在其中接收内部地址信号的冗余判断电路，并确定对应的地址是否对应于多个正常字线的有缺陷字线的地址， 以及地址计数器，用于产生用于顺序地刷新多个正常字线和冗余字线的刷新地址信号。 冗余判断电路在刷新时被停用。
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公开(公告)号：US07821862B2
公开(公告)日：2010-10-26
申请号：US11902877
申请日：2007-09-26
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
摘要翻译： 本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。 半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。 在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。
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公开(公告)号：US20060239103A1
公开(公告)日：2006-10-26
申请号：US11472252
申请日：2006-06-22
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
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公开(公告)号：US08223577B2
公开(公告)日：2012-07-17
申请号：US13067857
申请日：2011-06-30
IPC分类号： G11C8/00
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
摘要翻译： 本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。 半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。 在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。
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公开(公告)号：US20110261639A1
公开(公告)日：2011-10-27
申请号：US13067857
申请日：2011-06-30
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
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公开(公告)号：US20080253215A1
公开(公告)日：2008-10-16
申请号：US11902877
申请日：2007-09-26
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
摘要翻译： 本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。 半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。 在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。
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公开(公告)号：US07088636B2
公开(公告)日：2006-08-08
申请号：US11174604
申请日：2005-07-06
IPC分类号： G11C8/00
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
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