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公开(公告)号：US08473809B2
公开(公告)日：2013-06-25
申请号：US12839237
申请日：2010-07-19
申请人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
发明人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
CPC分类号： G11C11/5642 , G11C11/5628 , G11C29/00
摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.
摘要翻译： 本文描述了用于操作非易失性存储器的非易失性存储设备和技术。 一个实施例包括访问要编程到一组非易失性存储元件中的“n”页数据。 基于在“n”页数据上均匀分布读取错误的编码方案，将“n”个页映射到每个非易失性存储元件的数据状态。 基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。 编程可以包括同时对“n”页进行编程。 在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案和将重大故障模式（例如，数据保留错误）分配给 第二页。
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公开(公告)号：US20110126080A1
公开(公告)日：2011-05-26
申请号：US12839237
申请日：2010-07-19
申请人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
发明人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
CPC分类号： G11C11/5642 , G11C11/5628 , G11C29/00
摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.
摘要翻译： 本文描述了用于操作非易失性存储器的非易失性存储设备和技术。 一个实施例包括访问要编程到一组非易失性存储元件中的“n”页数据。 基于在“n”页数据上均匀分布读取错误的编码方案，将“n”个页映射到每个非易失性存储元件的数据状态。 基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。 编程可以包括同时对“n”页进行编程。 在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案和将重大故障模式（例如，数据保留错误）分配给 第二页。
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公开(公告)号：US07616499B2
公开(公告)日：2009-11-10
申请号：US11617541
申请日：2006-12-28
申请人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
发明人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence and if the number of bits in these regions is more than a pre-set the memory will fail verify status. A method of verifying data in a memory device includes the steps of: defining an retention margin between adjacent data thresholds; programming the memory device with data; determining whether bits are present in the data retention margin; and if the number of bits in the retention margin exceeds a threshold, generating an error.
摘要翻译： 提供了使用部分数据保留余量的存储器件中的数据验证。 从区域读取位计数，以确定错误是否会导致内存。 在正常程序验证序列之后执行在一个或多个保留边缘部分中的读取，并且如果这些区域中的位数大于预设，则存储器将失败验证状态。 验证存储器件中的数据的方法包括以下步骤：定义相邻数据阈值之间的保留余量; 使用数据对存储设备进行编程; 确定位是否存在于数据保留余量中; 并且如果保留余量中的比特数超过阈值，则产生错误。
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公开(公告)号：US07652918B2
公开(公告)日：2010-01-26
申请号：US11617546
申请日：2006-12-28
申请人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
发明人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.
摘要翻译： 一种存储器系统，包括分成逻辑块的存储元件阵列和所述逻辑块内的页面，并且提供管理电路。 管理电路与所述存储元件阵列通信并执行编程和读取操作。 编程操作包括编程多个多状态存储数据。 读取操作包括定义相邻数据阈值之间的保留余量，确定位是否存在于数据保留余量的一部分中，以及如果保留余量部分中的位数超过阈值，则产生错误。
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公开(公告)号：US20080158990A1
公开(公告)日：2008-07-03
申请号：US11617546
申请日：2006-12-28
申请人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
发明人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
IPC分类号： G11C16/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.
摘要翻译： 一种存储器系统，包括分成逻辑块的存储元件阵列和所述逻辑块内的页面，并且提供管理电路。 管理电路与所述存储元件阵列通信并执行编程和读取操作。 编程操作包括编程多个多状态存储数据。 读取操作包括定义相邻数据阈值之间的保留余量，确定位是否存在于数据保留余量的一部分中，以及如果保留余量部分中的位数超过阈值，则产生错误。
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公开(公告)号：US20080158989A1
公开(公告)日：2008-07-03
申请号：US11617541
申请日：2006-12-28
申请人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
发明人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
IPC分类号： G11C16/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence and if the number of bits in these regions is more than a pre-set the memory will fail verify status. A method of verifying data in a memory device includes the steps of: defining an retention margin between adjacent data thresholds; programming the memory device with data; determining whether bits are present in the data retention margin; and if the number of bits in the retention margin exceeds a threshold, generating an error.
摘要翻译： 提供了使用部分数据保留余量的存储器件中的数据验证。 从区域读取位计数，以确定错误是否会导致内存。 在正常程序验证序列之后执行在一个或多个保留边缘部分中的读取，并且如果这些区域中的位数大于预设，则存储器将失败验证状态。 验证存储器件中的数据的方法包括以下步骤：定义相邻数据阈值之间的保留余量; 使用数据对存储设备进行编程; 确定位是否存在于数据保留余量中; 并且如果保留余量中的比特数超过阈值，则产生错误。
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公开(公告)号：US08737125B2
公开(公告)日：2014-05-27
申请号：US13569008
申请日：2012-08-07
申请人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
发明人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/34
摘要： In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results.
摘要翻译： 在存储随机化数据的非易失性存储器阵列中，可以从单个读取步骤的聚合结果确定程序级 - 存储在存储器单元群中的每个存储单元的状态数。 用于聚合读取步骤的二进制结果的电路包括具有连接到保持二进制结果的数据锁存器的控制栅极的并行晶体管，使得通过组合晶体管的电流依赖于二进制结果。
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公开(公告)号：US20140043897A1
公开(公告)日：2014-02-13
申请号：US13569008
申请日：2012-08-07
申请人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
发明人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/34
摘要： In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results.
摘要翻译： 在存储随机化数据的非易失性存储器阵列中，可以从单个读取步骤的聚合结果确定程序级 - 存储在存储器单元群中的每个存储单元的状态数。 用于聚合读取步骤的二进制结果的电路包括具有连接到保持二进制结果的数据锁存器的控制栅极的并行晶体管，使得通过组合晶体管的电流依赖于二进制结果。
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公开(公告)号：US08843693B2
公开(公告)日：2014-09-23
申请号：US13109972
申请日：2011-05-17
申请人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-chien Kuo , Yee Lih Koh , Jun Wan
发明人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-chien Kuo , Yee Lih Koh , Jun Wan
CPC分类号： G11C16/3427 , G06F12/1408 , G11C7/1006 , G11C7/1012
摘要： A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block.
摘要翻译： 与存储器控制器协作的存储器件在将其存储在非易失性存储器单元阵列之前，使用所选择的加密密钥对每个数据单元进行加扰。 这有助于减少由特定数据模式的重复和长期存储引起的编程干扰，用户读取干扰和浮动栅极到浮动栅极耦合。 对于具有逻辑地址并用于存储在物理地址的给定页面的数据，从作为逻辑地址和物理地址的函数的有限序列中选择密钥。 在块管理方案中，存储器阵列被组织成擦除块，物理地址是每个块中的相对页号。 当逻辑地址分组为逻辑组并作为组操作并且每个组可存储到子块中时，物理地址是子块中的相对页号。
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公开(公告)号：US20120297111A1
公开(公告)日：2012-11-22
申请号：US13109972
申请日：2011-05-17
申请人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-Chien Kuo , Yee Lih Koh , Jun Wan
发明人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-Chien Kuo , Yee Lih Koh , Jun Wan
IPC分类号： G06F12/02
CPC分类号： G11C16/3427 , G06F12/1408 , G11C7/1006 , G11C7/1012
摘要： A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block.
摘要翻译： 与存储器控制器协作的存储器件在将其存储在非易失性存储器单元阵列之前，使用所选择的加密密钥对每个数据单元进行加扰。 这有助于减少由特定数据模式的重复和长期存储引起的程序干扰，用户读取干扰和浮动栅极到浮动栅极耦合。 对于具有逻辑地址并用于存储在物理地址的给定页面的数据，从作为逻辑地址和物理地址的函数的有限序列中选择密钥。 在块管理方案中，存储器阵列被组织成擦除块，物理地址是每个块中的相对页号。 当逻辑地址分组为逻辑组并作为组操作并且每个组可存储到子块中时，物理地址是子块中的相对页号。
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