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公开(公告)号：US20120269421A1
公开(公告)日：2012-10-25
申请号：US13533942
申请日：2012-06-26
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luogi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luogi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.
摘要翻译： 在一个方面，本发明涉及用于模拟，验证，检查，表征，确定和/或评估光刻设计，技术和/或系统的技术和系统，和/或由其执行的各个功能或使用的组件 其中。 在一个实施例中，本发明是加速光刻特性和/或性质的光刻模拟，检查，表征和/或评估以及光刻系统和处理技术的效果和/或相互作用的系统和方法。
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公开(公告)号：US08516405B2
公开(公告)日：2013-08-20
申请号：US13533942
申请日：2012-06-26
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.
摘要翻译： 在一个方面，本发明涉及用于模拟，验证，检查，表征，确定和/或评估光刻设计，技术和/或系统的技术和系统，和/或由其执行的各个功能或使用的组件 其中。 在一个实施例中，本发明是加速光刻特性和/或性质的光刻模拟，检查，表征和/或评估以及光刻系统和处理技术的效果和/或相互作用的系统和方法。
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公开(公告)号：US08209640B2
公开(公告)日：2012-06-26
申请号：US12964697
申请日：2010-12-09
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
摘要翻译： 这里描述和说明了许多发明。 在一个方面，本发明涉及用于模拟，验证，检查，表征，确定和/或评估光刻设计，技术和/或系统的技术和系统，和/或由其执行的各个功能或使用的组件 其中。 在一个实施例中，本发明是加速光刻特性和/或性质的光刻模拟，检查，表征和/或评估以及光刻系统和处理技术的效果和/或相互作用的系统和方法。 在这方面，在一个实施例中，本发明采用光刻仿真系统架构，包括特定于应用的硬件加速器，以及用于加速和促进掩模设计的验证，表征和/或检验的处理技术，例如RET设计 ，包括对整个光刻工艺进行详细的仿真和表征，以验证设计在最终的晶片图案上实现和/或提供期望的结果。 该系统包括：（1）通用目的型计算设备，用于执行在数据处理中具有分支和相互依赖性的基于案例的逻辑，以及（2）加速器子系统执行大部分计算密集型任务。
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公开(公告)号：US20070022402A1
公开(公告)日：2007-01-25
申请号：US11527010
申请日：2006-09-26
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
摘要翻译： 这里描述和说明了许多发明。 在一个方面，本发明涉及用于模拟，验证，检查，表征，确定和/或评估光刻设计，技术和/或系统的技术和系统，和/或由其执行的各个功能或使用的组件 其中。 在一个实施例中，本发明是加速光刻特性和/或性质的光刻模拟，检查，表征和/或评估以及光刻系统和处理技术的效果和/或相互作用的系统和方法。 在这方面，在一个实施例中，本发明采用光刻仿真系统架构，包括特定于应用的硬件加速器，以及用于加速和促进掩模设计的验证，表征和/或检验的处理技术，例如RET设计 ，包括对整个光刻工艺进行详细的仿真和表征，以验证设计在最终的晶片图案上实现和/或提供期望的结果。 该系统包括：（1）通用目的型计算设备，用于执行在数据处理中具有分支和相互依赖性的基于案例的逻辑，以及（2）加速器子系统执行大部分计算密集型任务。
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公开(公告)号：US07120895B2
公开(公告)日：2006-10-10
申请号：US11084484
申请日：2005-03-18
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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公开(公告)号：US07117477B2
公开(公告)日：2006-10-03
申请号：US11024121
申请日：2004-12-28
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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公开(公告)号：US07114145B2
公开(公告)日：2006-09-26
申请号：US10989972
申请日：2004-11-16
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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公开(公告)号：US20050166174A1
公开(公告)日：2005-07-28
申请号：US11084484
申请日：2005-03-18
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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公开(公告)号：US07111277B2
公开(公告)日：2006-09-19
申请号：US10981914
申请日：2004-11-04
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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公开(公告)号：US07117478B2
公开(公告)日：2006-10-03
申请号：US11037988
申请日：2005-01-18
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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