公开(公告)号：US20090055579A1

公开(公告)日：2009-02-26

申请号：US12230142

申请日：2008-08-25

申请人： June-hong Park ,  Jae-yong Jeong ,  Chi-weon Yoon

发明人： June-hong Park ,  Jae-yong Jeong ,  Chi-weon Yoon

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7202 ,  G11C11/5628 ,  G11C16/10 ,  G11C2216/14

摘要： Provided is a semiconductor memory device for simultaneously programming a plurality of banks. The semiconductor memory device includes: a memory cell array comprising a plurality of banks; a plurality of data buffers storing a plurality of pieces of program data to be programmed in the corresponding banks; and a plurality of scan latches configured to scan the plurality of program data transmitted from the corresponding data buffers, and configured to generate 1st through n−1th sub program data, n being a natural number greater than 2.

摘要翻译： 提供了一种用于同时编程多个存储体的半导体存储器件。 半导体存储器件包括：包括多个存储体的存储单元阵列; 多个数据缓冲器，存储要在对应的存储体中编程的多个程序数据; 以及多个扫描锁存器，被配置为扫描从相应的数据缓冲器发送的多个节目数据，并且被配置为生成第1到第n个第1个子节目数据，n是大于2的自然数。

公开(公告)号：US08189386B2

公开(公告)日：2012-05-29

申请号：US12458437

申请日：2009-07-13

申请人： June-hong Park ,  Chi-weon Yoon

发明人： June-hong Park ,  Chi-weon Yoon

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/00 ,  G11C2211/5621

摘要： A programming method for a non-volatile memory device includes performing a programming operation to program memory cells, when the programmed memory cells are determined to include memory cells that failed to be programmed and when a current program loop is a maximum program loop, determining whether a number of the memory cells that failed to be programmed corresponds to a number of memory cells that can successfully undergo ECC (error checking and correction), when the number of the memory cells that failed to be programmed is less than the number of the memory cells that can successfully undergo ECC, reading data so as to determine whether a number of error bits of the memory cells that failed to be programmed can successfully undergo ECC, and, when the memory cells that failed to be programmed can successfully undergo ECC, ending a programming operation.

摘要翻译： 用于非易失性存储器件的编程方法包括执行编程操作以对存储器单元进行编程，当编程存储器单元被确定为包括不能被编程的存储器单元以及当前程序循环是最大程序循环时，确定是否 当编程失败的存储器单元的数量小于存储器的数量时，未编程的多个存储器单元对应于可以成功地进行ECC（错误校验和校正）的多个存储器单元 可以成功进行ECC的单元，读取数据，以确定是否能够编程的存储器单元的错误位的数量是否能够成功地进行ECC，并且当未编程的存储器单元可以成功地进行ECC时，结束 一个编程操作。

公开(公告)号：US20100027336A1

公开(公告)日：2010-02-04

申请号：US12458437

申请日：2009-07-13

申请人： June-hong Park ,  Chi-weon Yoon

发明人： June-hong Park ,  Chi-weon Yoon

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/00 ,  G11C2211/5621

摘要： A programming method for a non-volatile memory device includes performing a programming operation to program memory cells, when the programmed memory cells are determined to include memory cells that failed to be programmed and when a current program loop is a maximum program loop, determining whether a number of the memory cells that failed to be programmed corresponds to a number of memory cells that can successfully undergo ECC (error checking and correction), when the number of the memory cells that failed to be programmed is less than the number of the memory cells that can successfully undergo ECC, reading data so as to determine whether a number of error bits of the memory cells that failed to be programmed can successfully undergo ECC, and, when the memory cells that failed to be programmed can successfully undergo ECC, ending a programming operation.

摘要翻译： 用于非易失性存储器件的编程方法包括执行编程操作以对存储器单元进行编程，当编程存储器单元被确定为包括不能被编程的存储器单元以及当前程序循环是最大程序循环时，确定是否 当编程失败的存储器单元的数量小于存储器的数量时，未编程的多个存储器单元对应于可以成功地进行ECC（错误校验和校正）的多个存储器单元 可以成功进行ECC的单元，读取数据，以确定是否能够编程的存储器单元的错误位的数量是否能够成功地进行ECC，并且当未编程的存储器单元可以成功地进行ECC时，结束 一个编程操作。

公开(公告)号：US07782680B2

公开(公告)日：2010-08-24

申请号：US12003589

申请日：2007-12-28

申请人： Kee-ho Jung ,  Jae-yong Jeong ,  Chi-weon Yoon

发明人： Kee-ho Jung ,  Jae-yong Jeong ,  Chi-weon Yoon

IPC分类号： G11C11/34

CPC分类号： G11C16/3454

摘要： A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a portion of the verify data buffer is selectively enabled as a verify data buffer or a program data buffer responsive to a buffer control signal.

摘要翻译： 闪速存储器件包括被配置为缓冲要在存储器单元阵列中编程的程序数据的程序数据缓冲器，以及配置为比较验证数据以确认程序数据是否被精确地编程在存储单元阵列中的校验数据缓冲器，其中， 验证数据缓冲器的至少一部分被有选择地启用为响应于缓冲器控制信号的验证数据缓冲器或程序数据缓冲器。

公开(公告)号：US07668015B2

公开(公告)日：2010-02-23

申请号：US12005366

申请日：2007-12-27

申请人： Jae-phil Kong ,  Heung-soo Lim ,  Jae-yong Jeong ,  Chi-weon Yoon

发明人： Jae-phil Kong ,  Heung-soo Lim ,  Jae-yong Jeong ,  Chi-weon Yoon

IPC分类号： G11C16/04

CPC分类号： G11C11/5628

摘要： In a method of driving a nonvolatile memory device a first data state is determined from among the plurality of data states. The number of simultaneously programmed bits is set according to the determined first data state and a scanning operation is performed on data input from an external device to search data bits to be programmed. The searched data bits are programmed in response to the number of simultaneously programmed bits. The number of simultaneously programmed bits corresponding to the first data state is different from a number of simultaneously programmed bits corresponding to at least a second of the plurality of data states.

摘要翻译： 在驱动非易失性存储器件的方法中，从多个数据状态中确定第一数据状态。 根据确定的第一数据状态来设置同时编程的位的数量，并且对从外部设备输入的数据执行扫描操作以搜索要编程的数据位。 搜索到的数据位被编程为响应于同时编程的位的数量。 对应于第一数据状态的同时被编程的位的数量与对应于多个数据状态中的至少一个数据状态的同时被编程的位的数量不同。

公开(公告)号：US20080170443A1

公开(公告)日：2008-07-17

申请号：US12003589

申请日：2007-12-28

申请人： Kee-ho Jung ,  Jae-yong Jeong ,  Chi-weon Yoon

发明人： Kee-ho Jung ,  Jae-yong Jeong ,  Chi-weon Yoon

IPC分类号： G11C16/06

CPC分类号： G11C16/3454

摘要： A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a portion of the verify data buffer is selectively enabled as a verify data buffer or a program data buffer responsive to a buffer control signal.

摘要翻译： 闪速存储器件包括被配置为缓冲要在存储器单元阵列中编程的程序数据的程序数据缓冲器，以及配置为比较验证数据以确认程序数据是否被精确地编程在存储单元阵列中的校验数据缓冲器，其中， 验证数据缓冲器的至少一部分被有选择地启用为响应于缓冲器控制信号的验证数据缓冲器或程序数据缓冲器。

公开(公告)号：US20080192540A1

公开(公告)日：2008-08-14

申请号：US12005366

申请日：2007-12-27

申请人： Jae-Phil Kong ,  Heung-soo Lim ,  Jae-yong Jeong ,  Chi-weon Yoon

发明人： Jae-Phil Kong ,  Heung-soo Lim ,  Jae-yong Jeong ,  Chi-weon Yoon

IPC分类号： G11C16/10

CPC分类号： G11C11/5628

摘要： In a method of driving a nonvolatile memory device a first data state is determined from among the plurality of data states. The number of simultaneously programmed bits is set according to the determined first data state and a scanning operation is performed on data input from an external device to search data bits to be programmed. The searched data bits are programmed in response to the number of simultaneously programmed bits. The number of simultaneously programmed bits corresponding to the first data state is different from a number of simultaneously programmed bits corresponding to at least a second of the plurality of data states.

摘要翻译： 在驱动非易失性存储器件的方法中，从多个数据状态中确定第一数据状态。 根据确定的第一数据状态来设置同时编程的位的数量，并且对从外部设备输入的数据执行扫描操作以搜索要编程的数据位。 搜索到的数据位被编程为响应于同时编程的位的数量。 对应于第一数据状态的同时被编程的位的数量与对应于多个数据状态中的至少一个数据状态的同时被编程的位的数量不同。

公开(公告)号：US08359424B2

公开(公告)日：2013-01-22

申请号：US12591198

申请日：2009-11-12

申请人： Jae-phil Kong ,  Chi-weon Yoon

发明人： Jae-phil Kong ,  Chi-weon Yoon

IPC分类号： G06F12/00

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C2211/5641

摘要： Provided are a flash memory device and a reading method of the flash memory device. A multi-level cell flash memory device includes: a memory cell array comprising main memory cells storing main data, and indicator cells storing indicate data indicating one of a first mode and a second mode in which the main data of the main memory cell, to which the indicate cells correspond, is written; and an output unit outputting in response to a control signal corresponding to the indicate data, one of main data read from the memory cell array and forced data forcing some bit values of the main data to bit values of mode specific data, as reading data.

摘要翻译： 提供了闪速存储装置和闪存装置的读取方法。 多级单元闪存器件包括：存储单元阵列，包括存储主数据的主存储单元，存储指示单元的指示单元表示指示主存储单元的主数据的第一模式和第二模式之一的数据， 指示单元对应的; 以及输出单元，响应于与指示数据相对应的控制信号，从存储器单元阵列读取的主数据中的一个和强制数据将主数据的某些位值强制为模式特定数据的位值作为读取数据。

公开(公告)号：US08347183B2

公开(公告)日：2013-01-01

申请号：US12486875

申请日：2009-06-18

申请人： Chi-weon Yoon ,  Chae-hoon Kim

发明人： Chi-weon Yoon ,  Chae-hoon Kim

IPC分类号： H03M13/00

CPC分类号： G06F11/1068 ,  G11C16/16 ,  G11C16/3454

摘要： A flash memory device using an error correction code (ECC) algorithm and a method of operating the same. The device includes a memory cell array including a error correction code (ECC) block including data memory cells configured to store data and a parity cell configured to store a first parity code, a parity controller configured to generate a second parity code based on a the current operating mode of the flash memory device, and an error correction unit configured to receive one of the first and second parity codes and to perform an ECC algorithm on the data stored in the data memory cells using the received parity code. A control logic restarts an erase operation on an erroneously unerased data memory cell or prevents the erase operation from being restarted based on the number of erroneous bits per ECC block.

摘要翻译： 一种使用纠错码（ECC）算法的闪存器件及其操作方法。 该设备包括存储单元阵列，其包括纠错码（ECC）块，该纠错码（ECC）块包括被配置为存储数据的数据存储器单元和被配置为存储第一奇偶校验码的奇偶校验单元，奇偶校验控制器被配置为基于 闪存器件的当前操作模式，以及错误校正单元，被配置为接收第一和第二奇偶校验码之一，并且使用所接收的奇偶校验码对存储在数据存储单元中的数据执行ECC算法。 一个控制逻辑重新启动一个错误的未故障的数据存储单元上的擦除操作，或者基于每个ECC块的错误位数来防止重新启动擦除操作。

公开(公告)号：US20090327839A1

公开(公告)日：2009-12-31

申请号：US12486875

申请日：2009-06-18

申请人： Chi-weon Yoon ,  Chae-hoon Kim

发明人： Chi-weon Yoon ,  Chae-hoon Kim

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1068 ,  G11C16/16 ,  G11C16/3454

摘要： A flash memory device using an error correction code (ECC) algorithm and a method of operating the same. The device includes a memory cell array including a error correction code (ECC) block including data memory cells configured to store data and a parity cell configured to store a first parity code, a parity controller configured to generate a second parity code based on a the current operating mode of the flash memory device, and an error correction unit configured to receive one of the first and second parity codes and to perform an ECC algorithm on the data stored in the data memory cells using the received parity code. A control logic restarts an erase operation on an erroneously unerased data memory cell or prevents the erase operation from being restarted based on the number of erroneous bits per ECC block.

摘要翻译： 一种使用纠错码（ECC）算法的闪存器件及其操作方法。 该设备包括存储单元阵列，其包括纠错码（ECC）块，该纠错码（ECC）块包括被配置为存储数据的数据存储器单元和被配置为存储第一奇偶校验码的奇偶校验单元，奇偶校验控制器被配置为基于 闪存器件的当前操作模式，以及错误校正单元，被配置为接收第一和第二奇偶校验码之一，并且使用所接收的奇偶校验码对存储在数据存储单元中的数据执行ECC算法。 一个控制逻辑重新启动一个错误的未故障的数据存储单元上的擦除操作，或者基于每个ECC块的错误位数来防止重新启动擦除操作。