Display substrate for easy detection of pattern misalignment
    1.
    发明授权
    Display substrate for easy detection of pattern misalignment 有权
    显示基板,便于检测图案不对准

    公开(公告)号:US08018542B2

    公开(公告)日:2011-09-13

    申请号:US11502915

    申请日:2006-08-10

    IPC分类号: G02F1/1333

    摘要: A display substrate includes a base substrate, a conductive line on the base substrate, a switching element and a testing member. The switching element includes a first electrode formed on the semiconductor layer pattern and electrically connected to the conductive line, and a second electrode spaced apart from the first electrode and semiconductor layer pattern. The testing member includes a conductive line testing portion that is formed from the same layer as the conductive line and an electrode testing portion that is formed from the same layer as the first electrode. The conductive line testing portion and the electrode testing portion have substantially the same width as the conductive line and the first electrode, respectively. The testing member also includes a semiconductor layer testing portion. The display substrate lends itself to efficient manufacturing with reduced process time and cost.

    摘要翻译: 显示基板包括基底基板,基底基板上的导线,开关元件和测试部件。 开关元件包括形成在半导体层图案上并电连接到导电线的第一电极和与第一电极和半导体层图案间隔开的第二电极。 测试构件包括由与导电线相同的层形成的导线测试部分和由与第一电极相同的层形成的电极测试部分。 导线测试部分和电极测试部分分别具有与导电线和第一电极基本上相同的宽度。 测试构件还包括半导体层测试部分。 显示基板有助于有效的制造,缩短了处理时间和成本。

    Display substrate for easy detection of pattern misalignment
    2.
    发明申请
    Display substrate for easy detection of pattern misalignment 有权
    显示基板,便于检测图案不对准

    公开(公告)号:US20070034522A1

    公开(公告)日:2007-02-15

    申请号:US11502915

    申请日:2006-08-10

    IPC分类号: C25B1/34

    摘要: A display substrate includes a base substrate, a conductive line on the base substrate, a switching element and a testing member. The switching element includes a first electrode formed on the semiconductor layer pattern and electrically connected to the conductive line, and a second electrode spaced apart from the first electrode and semiconductor layer pattern. The testing member includes a conductive line testing portion that is formed from the same layer as the conductive line and an electrode testing portion that is formed from the same layer as the first electrode. The conductive line testing portion and the electrode testing portion have substantially the same width as the conductive line and the first electrode, respectively. The testing member also includes a semiconductor layer testing portion. The display substrate lends itself to efficient manufacturing with reduced process time and cost.

    摘要翻译: 显示基板包括基底基板,基底基板上的导线,开关元件和测试部件。 开关元件包括形成在半导体层图案上并电连接到导电线的第一电极和与第一电极和半导体层图案间隔开的第二电极。 测试构件包括由与导电线相同的层形成的导线测试部分和由与第一电极相同的层形成的电极测试部分。 导线测试部分和电极测试部分分别具有与导电线和第一电极基本上相同的宽度。 测试构件还包括半导体层测试部分。 显示基板有助于有效的制造,缩短了处理时间和成本。

    Thin film transistor array panel and manufacturing method thereof
    3.
    发明申请
    Thin film transistor array panel and manufacturing method thereof 有权
    薄膜晶体管阵列面板及其制造方法

    公开(公告)号:US20050082535A1

    公开(公告)日:2005-04-21

    申请号:US10926719

    申请日:2004-08-26

    CPC分类号: G02F1/1368 G02F1/1339

    摘要: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

    摘要翻译: 提供一种制造薄膜晶体管阵列面板的方法,包括:在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜,下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极,所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

    Method of manufacturing a thin film transistor array panel
    4.
    发明授权
    Method of manufacturing a thin film transistor array panel 有权
    制造薄膜晶体管阵列面板的方法

    公开(公告)号:US07459323B2

    公开(公告)日:2008-12-02

    申请号:US11512805

    申请日:2006-08-30

    IPC分类号: H01L21/00

    CPC分类号: G02F1/1368 G02F1/1339

    摘要: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

    摘要翻译: 提供一种制造薄膜晶体管阵列面板的方法,包括:在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜,下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极,所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

    Thin film transistor array panel and manufacturing method thereof
    6.
    发明申请
    Thin film transistor array panel and manufacturing method thereof 有权
    薄膜晶体管阵列面板及其制造方法

    公开(公告)号:US20060289965A1

    公开(公告)日:2006-12-28

    申请号:US11512805

    申请日:2006-08-30

    CPC分类号: G02F1/1368 G02F1/1339

    摘要: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

    摘要翻译: 提供一种制造薄膜晶体管阵列面板的方法,包括:在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜,下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极,所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。