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    Process variation tolerant memory design
    2.
    发明授权
    Process variation tolerant memory design 有权
    过程变异容忍存储器设计

    公开(公告)号：US07979832B2

    公开(公告)日：2011-07-12

    申请号：US11873638

    申请日：2007-10-17

    申请人： Seong-Ook Jung ,  Sei Seung Yoon ,  Hyunwoo Nho

    发明人： Seong-Ook Jung ,  Sei Seung Yoon ,  Hyunwoo Nho

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5036 ,  G06F17/5045 ,  G06F2217/10

    摘要： Methods and systems for designing process variation tolerant memory are disclosed. A memory circuit is divided into functional blocks. A statistical distribution is calculated for each of the functional blocks. Then, the distributions of each block are combined to verify a credibility of the circuit. The credibility is verified if the circuit meets a predetermined yield.

    摘要翻译： 公开了用于设计过程变化容限存储器的方法和系统。 存储电路分为功能块。 计算每个功能块的统计分布。 然后，组合每个块的分布，以验证电路的可信度。 如果电路满足预定的收益率，则验证可信度。

    Process Variation Tolerant Memory Design
    4.
    发明申请
    Process Variation Tolerant Memory Design 有权
    过程变异容错设计

    公开(公告)号：US20080141190A1

    公开(公告)日：2008-06-12

    申请号：US11873638

    申请日：2007-10-17

    申请人： Seong-Ook Jung ,  Sei Seung Yoon ,  Hyunwoo Nho

    发明人： Seong-Ook Jung ,  Sei Seung Yoon ,  Hyunwoo Nho

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/5045 ,  G06F2217/10

    摘要： Methods and systems for designing process variation tolerant memory are disclosed. A memory circuit is divided into functional blocks. A statistical distribution is calculated for each of the functional blocks. Then, the distributions of each block are combined to verify a credibility of the circuit. The credibility is verified if the circuit meets a predetermined yield.

    摘要翻译： 公开了用于设计过程变化容限存储器的方法和系统。 存储电路分为功能块。 计算每个功能块的统计分布。 然后，组合每个块的分布，以验证电路的可信度。 如果电路满足预定的收益率，则验证可信度。

    Nonlinear pulse-width-modulated clock generation
    6.
    发明授权
    Nonlinear pulse-width-modulated clock generation 有权

    公开(公告)号：US10319278B1

    公开(公告)日：2019-06-11

    申请号：US15251920

    申请日：2016-08-30

    申请人： Hyunwoo Nho ,  Mohammad B. Vahid Far ,  Xiaofeng Wang

    发明人： Hyunwoo Nho ,  Mohammad B. Vahid Far ,  Xiaofeng Wang

    IPC分类号： G09G3/20

    摘要： Systems and methods are provided for generating a nonlinear clock signal. Such a signal may be used to drive sub-pixels of an electronic display. The electronic display may include a microdriver that drives at least one sub-pixel based at least in part on an image data signal and an emission clock signal. The image data signal specifies a gray level for driving the sub-pixel and the emission clock signal includes a series of pulses of monotonically increasing pulse widths to enable the microdriver to drive the sub-pixel to emit light for a particular amount of time associated with the gray level. An emission timing controller may generate the emission clock signal.

    MITIGATION OF TEARING FROM INTRA-FRAME PAUSE
    7.
    发明申请
    MITIGATION OF TEARING FROM INTRA-FRAME PAUSE 有权

    公开(公告)号：US20230084423A1

    公开(公告)日：2023-03-16

    申请号：US17853649

    申请日：2022-06-29

    申请人： Apple Inc.

    发明人： Myungjoon Choi ,  Jie Won Ryu ,  Hyunwoo Nho ,  Xiaokai Li ,  Kaikai Guo ,  Szu-Hsien Lee ,  Rungrot Kitsomboonloha ,  Pei-En Chang ,  Amit Nayyar ,  Vehbi Calayir

    IPC分类号： G09G3/20 ,  G06F3/041

    摘要： Embodiments presented herein relate to reducing visual artifacts on an electronic display caused by an intra-frame pause. To do so, the intra-frame pause may be divided into smaller intra-frame pause segments. The intra-frame pause segments may be applied to the display during different image frames and/or at different locations on the electronic display. For example, each intra-frame pause segment may be applied to a different location on the electronic display. In some embodiments, multiple intra-frame pause segments may be applied during a single image frame. In some embodiments, the intra-frame pause segments may be applied to various image frames and at various location on the electronic display according to a pattern. To reduce band flickering that may be caused by the different locations of the intra-frame pause segments, an emission duty of one or more rows of pixels of the display may be adjusted.

    Mitigation of tearing from intra-frame pause
    8.
    发明授权
    Mitigation of tearing from intra-frame pause 有权

    公开(公告)号：US11605330B1

    公开(公告)日：2023-03-14

    申请号：US17853649

    申请日：2022-06-29

    申请人： Apple Inc.

    发明人： Myungjoon Choi ,  Jie Won Ryu ,  Hyunwoo Nho ,  Xiaokai Li ,  Kaikai Guo ,  Szu-Hsien Lee ,  Rungrot Kitsomboonloha ,  Pei-En Chang ,  Amit Nayyar ,  Vehbi Calayir

    IPC分类号： G09G3/20 ,  G06F3/041

    摘要： Embodiments presented herein relate to reducing visual artifacts on an electronic display caused by an intra-frame pause. To do so, the intra-frame pause may be divided into smaller intra-frame pause segments. The intra-frame pause segments may be applied to the display during different image frames and/or at different locations on the electronic display. For example, each intra-frame pause segment may be applied to a different location on the electronic display. In some embodiments, multiple intra-frame pause segments may be applied during a single image frame. In some embodiments, the intra-frame pause segments may be applied to various image frames and at various location on the electronic display according to a pattern. To reduce band flickering that may be caused by the different locations of the intra-frame pause segments, an emission duty of one or more rows of pixels of the display may be adjusted.

    Low-flicker variable refresh rate display
    9.
    发明授权
    Low-flicker variable refresh rate display 有权

    公开(公告)号：US11468809B2

    公开(公告)日：2022-10-11

    申请号：US14591354

    申请日：2015-01-07

    申请人： Apple Inc.

    发明人： Hyunwoo Nho ,  Wei Chen ,  Wei H Yao ,  Yafei Bi

    IPC分类号： G09G3/20

    摘要： An electronic device may have a variable refresh rate display. Static content may be displayed on the display at a lower refresh rate than moving content to conserve power. The display may include an array of pixels. Display driver circuitry in the display may load image data into rows of the pixels. The display driver circuitry may have digital-to-analog converter circuitry that supplies data signals to the array. The display driver circuitry may respond to a variable refresh rate control signal that is asserted and deasserted depending on whether static or moving image content is to be displayed. The display driver circuitry may use the digital-to-analog converter circuitry to apply a time-varying scaling factor to the image data. The magnitude of the scaling factor may be adjusted during transitions between refresh rates to help suppress luminance variations that might otherwise result in flickering on the display.