公开(公告)号：US5317573A

公开(公告)日：1994-05-31

申请号：US839678

申请日：1992-02-24

申请人： Orest Bula ,  Garrett S. Koch ,  Justin A. Woyke ,  Richard S. Gomez

发明人： Orest Bula ,  Garrett S. Koch ,  Justin A. Woyke ,  Richard S. Gomez

IPC分类号： G01R31/3193 ,  G06F11/22 ,  G11C29/00 ,  G11C29/40 ,  G11C29/44 ,  G11C29/56

CPC分类号： G11C29/72 ,  G11C29/56 ,  G01R31/31935 ,  G06F11/2205

摘要： Fail information from testing of a DUT memory array is captured and compressed by utilizing a compression matrix which is related in size to the available redundancy associated with the DUT (device under test) memory array, and which, in essence, defines the limits of redundancy repair. The compression matrix includes a plurality of matrix cells fewer in number than the number of memory cells in the DUT memory array and is arranged in a matrix of compression rows and compression columns, the number R of compression rows in the compression matrix being equal to (a predetermined number of redundant rows in the memory array) times (a predetermined number of redundant memory columns+1), and the number C of compression columns in the compression matrix being equal to (a predetermined number of redundant memory columns) times (a predetermined number of redundant memory rows+1). The compression matrix is loaded with the fail information concurrently with testing of the DUT memory array.

摘要翻译： 通过利用与DUT（被测设备）存储器阵列相关联的可用冗余大小相关的压缩矩阵来捕获和压缩来自测试DUT存储器阵列的故障信息，并且其实质上限定了冗余限制 修理。 压缩矩阵包括多个矩阵单元，其数量少于DUT存储器阵列中的存储器单元的数量，并且被排列成压缩行和压缩列的矩阵，压缩矩阵中的压缩行数R等于 存储器阵列中的预定数量的冗余行）乘以（预定数量的冗余存储器列+ 1），并且压缩矩阵中的压缩列数C等于（预定数量的冗余存储器列）次（a 预定数量的冗余存储器行+ 1）。 压缩矩阵与DUT存储器阵列的测试同时加载失败信息。

公开(公告)号：US5093584A

公开(公告)日：1992-03-03

申请号：US681626

申请日：1991-05-06

申请人： Justin A. Woyke ,  Orest Bula ,  Garrett S. Koch ,  Richard S. Gomez

发明人： Justin A. Woyke ,  Orest Bula ,  Garrett S. Koch ,  Richard S. Gomez

IPC分类号： H03K5/00 ,  H03K5/13 ,  H03L7/00

CPC分类号： H03L7/00 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00104 ,  H03K2005/00195

摘要： A clock circuit, together with a control current generator and a ratio circuit coupled thereto. The ratio circuit, of the invention, utilizes at least two capacitors each of which is coupled in series with a respective transistor and arranged in parallel with one another. Each capacitor transistor transistor pair is in parallel to the other and coupled between the control current generator and ground so that at least one of the transistors in a selected capacitor transistor series can be selectively turned off while the other can be directly controlled by the clock cycle. This circuit, generates timing edges within a clock cycle which timing edges can be any fraction of the clock cycle, and comprises a clock, a controlled current generator, and a ratio circuit coupled to the clock and the generator. Preferably this ratio circuit comprises at least two capacitor-transistor pairs coupled in parallel between the generator and ground with the clock being coupled to the control electrode of one of the transistors and being coupled to the control electrode of the other transistor together with a turn-off signal source. An element for discharging the capacitors is included in the circuit.

摘要翻译： 时钟电路与控制电流发生器和与其耦合的比率电路。 本发明的比率电路利用至少两个电容器，每个电容器与相应的晶体管串联耦合并且彼此并联布置。 每个电容晶体管晶体管对与另一个并联并耦合在控制电流发生器和地之间，使得所选择的电容器晶体管串联中的至少一个晶体管可以选择性地截止，而另一个可以由时钟周期直接控制 。 该电路在时钟周期内产生定时边沿，该时钟周期可以是时钟周期的任何一部分，并且包括时钟，受控电流发生器和耦合到时钟和发生器的比率电路。 优选地，该比率电路包括在发生器和地之间并联耦合的至少两个电容 - 晶体管对，其中时钟被耦合到晶体管之一的控制电极，并连接到另一个晶体管的控制电极， 关闭信号源。 用于放电电容器的元件包括在电路中。