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1.发明授权Apparatus and method for real time data error capture and compression redundancy analysis 失效用于实时数据错误捕获和压缩冗余分析的装置和方法
公开(公告)号：US5317573A
公开(公告)日：1994-05-31
申请号：US839678
申请日：1992-02-24
申请人： Orest Bula , Garrett S. Koch , Justin A. Woyke , Richard S. Gomez
发明人： Orest Bula , Garrett S. Koch , Justin A. Woyke , Richard S. Gomez
CPC分类号： G11C29/72 , G11C29/56 , G01R31/31935 , G06F11/2205
摘要： Fail information from testing of a DUT memory array is captured and compressed by utilizing a compression matrix which is related in size to the available redundancy associated with the DUT (device under test) memory array, and which, in essence, defines the limits of redundancy repair. The compression matrix includes a plurality of matrix cells fewer in number than the number of memory cells in the DUT memory array and is arranged in a matrix of compression rows and compression columns, the number R of compression rows in the compression matrix being equal to (a predetermined number of redundant rows in the memory array) times (a predetermined number of redundant memory columns+1), and the number C of compression columns in the compression matrix being equal to (a predetermined number of redundant memory columns) times (a predetermined number of redundant memory rows+1). The compression matrix is loaded with the fail information concurrently with testing of the DUT memory array.
摘要翻译： 通过利用与DUT（被测设备）存储器阵列相关联的可用冗余大小相关的压缩矩阵来捕获和压缩来自测试DUT存储器阵列的故障信息，并且其实质上限定了冗余限制 修理。 压缩矩阵包括多个矩阵单元，其数量少于DUT存储器阵列中的存储器单元的数量，并且被排列成压缩行和压缩列的矩阵，压缩矩阵中的压缩行数R等于 存储器阵列中的预定数量的冗余行）乘以（预定数量的冗余存储器列+ 1），并且压缩矩阵中的压缩列数C等于（预定数量的冗余存储器列）次（a 预定数量的冗余存储器行+ 1）。 压缩矩阵与DUT存储器阵列的测试同时加载失败信息。
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公开(公告)号：US5093584A
公开(公告)日：1992-03-03
申请号：US681626
申请日：1991-05-06
申请人： Justin A. Woyke , Orest Bula , Garrett S. Koch , Richard S. Gomez
发明人： Justin A. Woyke , Orest Bula , Garrett S. Koch , Richard S. Gomez
CPC分类号： H03L7/00 , H03K5/133 , H03K2005/00065 , H03K2005/00104 , H03K2005/00195
摘要： A clock circuit, together with a control current generator and a ratio circuit coupled thereto. The ratio circuit, of the invention, utilizes at least two capacitors each of which is coupled in series with a respective transistor and arranged in parallel with one another. Each capacitor transistor transistor pair is in parallel to the other and coupled between the control current generator and ground so that at least one of the transistors in a selected capacitor transistor series can be selectively turned off while the other can be directly controlled by the clock cycle. This circuit, generates timing edges within a clock cycle which timing edges can be any fraction of the clock cycle, and comprises a clock, a controlled current generator, and a ratio circuit coupled to the clock and the generator. Preferably this ratio circuit comprises at least two capacitor-transistor pairs coupled in parallel between the generator and ground with the clock being coupled to the control electrode of one of the transistors and being coupled to the control electrode of the other transistor together with a turn-off signal source. An element for discharging the capacitors is included in the circuit.
摘要翻译： 时钟电路与控制电流发生器和与其耦合的比率电路。 本发明的比率电路利用至少两个电容器，每个电容器与相应的晶体管串联耦合并且彼此并联布置。 每个电容晶体管晶体管对与另一个并联并耦合在控制电流发生器和地之间，使得所选择的电容器晶体管串联中的至少一个晶体管可以选择性地截止，而另一个可以由时钟周期直接控制 。 该电路在时钟周期内产生定时边沿，该时钟周期可以是时钟周期的任何一部分，并且包括时钟，受控电流发生器和耦合到时钟和发生器的比率电路。 优选地，该比率电路包括在发生器和地之间并联耦合的至少两个电容 - 晶体管对，其中时钟被耦合到晶体管之一的控制电极，并连接到另一个晶体管的控制电极， 关闭信号源。 用于放电电容器的元件包括在电路中。
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公开(公告)号：US07257247B2
公开(公告)日：2007-08-14
申请号：US09683836
申请日：2002-02-21
申请人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
发明人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
IPC分类号： G06K9/00
CPC分类号： G03F1/84
摘要： An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.
摘要翻译： 提出了一种用于分析半导体制造过程中的掩模缺陷的自动化系统。 该系统将来自检查工具的结果和来自被检查的每个掩模层的设计数据存储库的设计布局数据与计算机程序和预定规则集相结合，以确定给定掩模层上的缺陷何时发生。 掩模检查结果包括缺陷的存在，位置和类型（透明或不透明）。 最终，根据缺陷是否可能导致产品故障，确定是否废除，修理或接受给定的掩模。 将缺陷检查数据应用于被检查的每个掩模层的设计布局数据防止当所识别的缺陷不在掩模的关键区域时被报废。
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公开(公告)号：US06577406B2
公开(公告)日：2003-06-10
申请号：US09683551
申请日：2002-01-17
申请人： James A. Bruce , Orest Bula , Emily E. Fisch
发明人： James A. Bruce , Orest Bula , Emily E. Fisch
IPC分类号： G01B1100
CPC分类号： G03F7/70641
摘要： A control target structure and method for monitoring the lithographic affects on minimum feature in a lithographic process. The control target uses line array elements having a nominal width. By changing the shape of the line-ends of the elements the control target can be optimized for controlling either focus or dose.
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公开(公告)号：US07492940B2
公开(公告)日：2009-02-17
申请号：US11761856
申请日：2007-06-12
申请人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
发明人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
IPC分类号： G06K9/00
CPC分类号： G03F1/84
摘要： An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.
摘要翻译： 提出了一种用于分析半导体制造过程中的掩模缺陷的自动化系统。 该系统将来自检查工具的结果和来自被检查的每个掩模层的设计数据存储库的设计布局数据与计算机程序和预定规则集相结合，以确定何时发生了给定掩模层上的缺陷。 掩模检查结果包括缺陷的存在，位置和类型（透明或不透明）。 最终，根据缺陷是否可能导致产品故障，确定是否废除，修理或接受给定的掩模。 将缺陷检查数据应用于被检查的每个掩模层的设计布局数据防止当所识别的缺陷不在掩模的关键区域时被报废。
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公开(公告)号：US06704695B1
公开(公告)日：2004-03-09
申请号：US09354879
申请日：1999-07-16
IPC分类号： G06G748
CPC分类号： G03F1/36
摘要： A method and structure for creating a photomask data set includes inputting a design data set, creating a simulated printed data set by applying a lithography simulation model to chosen levels of the design data set, merging each chosen level of the design data set with each corresponding level of the simulated printed data set in order to produce a merged design data set, applying at least one test to the merged design data set, correcting the design data set based on results of the test to produce a corrected design data set, repeating the creating of the simulated printed data, merging, applying the test and correcting using the corrected design data set until the corrected design data set passes the test, and outputting the corrected design data set as the photomask data set.
摘要翻译： 一种用于创建光掩模数据集的方法和结构，包括输入设计数据集，通过将光刻仿真模型应用于设计数据集的选定级别来创建模拟印刷数据集，将每个选定级别的设计数据集与每个相应的 水平的模拟印刷数据集合，以便产生合并的设计数据集，对合并的设计数据集应用至少一个测试，基于测试结果校正设计数据集，以产生校正的设计数据集，重复 创建模拟打印数据，合并，应用测试并使用校正后的设计数据集进行校正，直到校正后的设计数据集通过测试，并输出校正后的设计数据集作为光掩模数据集。
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公开(公告)号：US06667136B2
公开(公告)日：2003-12-23
申请号：US10200912
申请日：2002-07-22
IPC分类号： G03F900
摘要： A method and structure for a photomask that includes a substrate having a first transmittance, a first pattern to be transferred to a photosensitive layer (the first pattern having a second transmittance lower than the first transmittance) and a second pattern having a third transmittance greater than the second transmittance and less than the first transmittance. The second pattern is adjacent at least a portion of the first pattern, and the substrate and the second pattern transmit light substantially in phase.
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8.发明授权Error checking of simulated printed images with process window effects included 有权对包含过程窗口效应的模拟打印图像进行错误检查公开(公告)号：US06373975B1
公开(公告)日：2002-04-16
申请号：US09237148
申请日：1999-01-25
IPC分类号： G06K900
CPC分类号： G06T7/0006 , G03F1/36 , G06T2207/30148
摘要： A structure and method for checking semiconductor designs for design rule violations includes generating a predicted printed structure (i.e., an ideal image) based on the semiconductor designs, altering the ideal image to include potential manufacturing variations, thereby producing at least two production images representing different manufacturing qualities, and comparing the production images to the design rules to produce an error list.
摘要翻译： 用于检查用于设计规则违规的半导体设计的结构和方法包括基于半导体设计产生预测的印刷结构（即，理想图像），改变理想图像以包括潜在的制造变化，由此产生至少两个代表不同的生产图像 制造质量，并将生产图像与设计规则进行比较以产生错误列表。
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公开(公告)号：US06238850B1
公开(公告)日：2001-05-29
申请号：US09379454
申请日：1999-08-23
IPC分类号： G03C500
CPC分类号： G03F7/70433 , G03F7/203 , G03F7/70466
摘要： A method of forming an image having reduced comer rounding in a photoresist layer is provided which comprises exposing a photoresist layer to a first mask having a first image, said first image having at least two edges; exposing said photoresist layer to a second mask having a second image, said second image having at least two edges, the second image edges being substantially rotated relative to the first image edges to produce a latent image in said photoresist layer having edges substantially rotated relative to the first and second image edges; and developing the photoresist layer to produce said image.
摘要翻译： 提供了一种在光致抗蚀剂层中形成具有减角的图像的方法，其包括将光致抗蚀剂层暴露于具有第一图像的第一掩模，所述第一图像具有至少两个边缘; 将所述光致抗蚀剂层暴露于具有第二图像的第二掩模，所述第二图像具有至少两个边缘，所述第二图像边缘相对于所述第一图像边缘基本旋转，以在所述光致抗蚀剂层中产生潜像，所述潜像基本上相对于 第一和第二图像边缘; 并显影光致抗蚀剂层以产生所述图像。
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公开(公告)号：US06627361B2
公开(公告)日：2003-09-30
申请号：US09901241
申请日：2001-07-09
IPC分类号： G03F900
摘要： An assist feature is formed on a lithographic reticle or mask using a hybrid resist and an exposure dose such that only an annular area is effectively exposed having a width that is potentially less than the minimum feature size that can be resolved by the mask exposure tool to simultaneously or sequentially form both a feature of interest and an assist feature for enhancing imaging of the feature of interest when the feature is printed to a wafer. Since the assist feature can be imaged simultaneously with the feature of interest or multiple assist features imaged concurrently, possibly between closely spaced features, data volume and mask writing time are greatly reduced. The invention is particularly applicable to the scaling of contact holes for connections to active devices in extremely high density integrated circuits.
摘要翻译： 使用混合抗蚀剂和曝光剂量在光刻掩模版或掩模上形成辅助特征，使得只有环形区域被有效地暴露，其宽度可能小于可由掩模曝光工具解析的最小特征尺寸， 同时或顺序地形成感兴趣的特征和当将特征印刷到晶片时增强感兴趣特征的成像的辅助特征。 由于可以与感兴趣的特征或同时成像的多个辅助特征（可能在紧密间隔的特征之间）同时成像辅助特征，所以数据量和掩模写入时间被大大减少。 本发明特别适用于用于连接到极高密度集成电路中的有源器件的接触孔的缩放。
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