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公开(公告)号：US06492838B2
公开(公告)日：2002-12-10
申请号：US09833512
申请日：2001-04-11
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： In one embodiment, a circuit is provided that includes a precharge device, a DNG FET transistor, and at least one pull-down FET transistor with a floating body. The precharge device is connected to a precharge node for charging it during a precharge state. The DNG FET transistor is connected between a DNG node and a charge sink for operably linking the DNG node to the charge sink during an evaluate state. In addition, the DNG transistor has an associated precharge leakage current. The at least one pull-down FET transistor has an input threshold voltage whose value is inversely affected by its floating body voltage. The at least one pull-down transistor is connected between the precharge node and the DNG node for discharging the precharge node during the evaluate state if so dictated by logical function input values applied to the pull-down transistors during the evaluate state. The DNG leakage current, during the precharge state, draws a sufficient amount of charge from the DNG node to maintain the at least one pull-down transistor body voltage(s) at a sufficiently low value so that the precharge node does not wrongfully evaluate to a discharge level during the evaluate state.
摘要翻译： 在一个实施例中，提供了一种包括预充电装置，DNG FET晶体管和至少一个具有浮动体的下拉式FET晶体管的电路。 预充电装置连接到预充电节点，用于在预充电状态下对其充电。 DNG FET晶体管连接在DNG节点和充电接收器之间，用于在评估状态期间可操作地将DNG节点连接到充电接收器。 此外，DNG晶体管具有相关的预充电漏电流。 所述至少一个下拉式FET晶体管具有其值受其浮动体电压反向影响的输入阈值电压。 至少一个下拉晶体管连接在预充电节点和DNG节点之间，用于在评估状态期间放电预充电节点，如果在评估状态期间由施加到下拉晶体管的逻辑功能输入值决定。 在预充电状态期间，DNG泄漏电流从DNG节点吸取足够量的电荷，以将至少一个下拉晶体管体电压维持在足够低的值，使得预充电节点不会错误地评估为 评估状态下的排放水平。
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2.发明授权High reliability triple redundant memory element with integrated testability and voting structures on each latch 失效高可靠性三重冗余存储元件，具有集成的可测试性和每个锁存器的投票结构公开(公告)号：US07027333B2
公开(公告)日：2006-04-11
申请号：US10934035
申请日：2004-09-03
申请人： John T. Petersen , Hassan Naser , Jonathan P Lotz
发明人： John T. Petersen , Hassan Naser , Jonathan P Lotz
CPC分类号： G11C11/4125
摘要： In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.
摘要翻译： 在优选实施例中，本发明提供了具有集成可测性的高可靠性三重冗余锁存器的电路和方法。 三个可设置的存储器元件将相同的逻辑值设置到每个可设置的存储器元件中。 在可设置的存储器元件被设置之后，具有来自第一，第二和第三可设置存储器元件的输入的三个投票结构确定保持在每个可设置存储元件上的逻辑值。 数据可以被扫描进出第二可设定存储元件。 数据通过缓冲器传播到第三可设置的存储元件中。 第三可设置存储元件可用于从三重冗余锁存器中扫描数据。 通过锁存器的传播延迟是三重冗余锁存器的唯一传播延迟。
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3.发明授权High reliability triple redundant latch with voting logic on each storage node 失效每个存储节点上具有投票逻辑的高可靠性三重冗余锁存器公开(公告)号：US06937527B1
公开(公告)日：2005-08-30
申请号：US10856557
申请日：2004-05-27
CPC分类号： H03K3/0375
摘要： In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.
摘要翻译： 在优选实施例中，本发明提供了一种用于高可靠性三重冗余锁存器的电路和方法。 三个可设置的存储器元件将相同的逻辑值设置到每个可设置的存储器元件中。 在可设置的存储器元件被设置之后，具有来自第一，第二和第三可设置存储器元件的输入的三个投票结构以及对可设置的存储器元件的控制确定保持在可设置的存储器元件上的逻辑值。 通过锁存器的传播延迟是三重冗余锁存器的唯一传播延迟。
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公开(公告)号：US06930527B1
公开(公告)日：2005-08-16
申请号：US10769337
申请日：2004-01-30
CPC分类号： H03K3/0375
摘要： In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch with storage node recovery. An input driver is connected to the input of three transfer gates. The output of each transfer gate is connected to a separate output of one of three feedback inverters. The transfer gates are controlled by two control inputs. The inputs of the three feedback inverters are connected the output of the forward inverter/majority voter. The output from each of the three feedback inverters are inputs to the forward inverter/majority voter. The output of the forward inverter/majority voter is connected to the input of the output driver. The output of the output driver is the output of the triple redundant latch.
摘要翻译： 在优选实施例中，本发明提供了一种用于具有存储节点恢复的较小且更快的三重冗余锁存器的电路和方法。 输入驱动器连接到三个传输门的输入端。 每个传输门的输出连接到三个反馈逆变器之一的单独输出。 传输门由两个控制输入控制。 三个反馈逆变器的输入端连接在正向逆变器/多数选择器的输出端。 三个反馈逆变器中的每一个的输出是正向逆变器/多数选择器的输入。 正向逆变器/多数选择器的输出端连接到输出驱动器的输入端。 输出驱动器的输出是三重冗余锁存器的输出。
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公开(公告)号：US07215581B2
公开(公告)日：2007-05-08
申请号：US10825398
申请日：2004-04-14
CPC分类号： H03K3/0375
摘要： In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the third settable memory element. The propagation delay through the third settable memory element is the only propagation delay of the triple redundant latch.
摘要翻译： 在优选实施例中，本发明提供了一种用于更小和更快的三重冗余锁存器的电路和方法。 三个可设置的存储器元件将相同的逻辑值设置到每个可设置的存储器元件中。 在可设置的存储器元件被设置之后，具有来自第一可设定存储元件，第二存储器元件的输入和对可设置存储器元件的控制的投票结构确定保持在第三可设置存储器元件上的逻辑值。 通过第三可设置存储元件的传播延迟是三重冗余锁存器的唯一传播延迟。
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公开(公告)号：US07054203B2
公开(公告)日：2006-05-30
申请号：US10834627
申请日：2004-04-28
IPC分类号： G11C7/10
CPC分类号： H03K3/0375
摘要： In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Two settable memory elements, and a voting structure/settable memory element set an identical logical value into each settable memory element, and the voting structure/settable memory element. After the settable memory elements, and the voting structure/settable memory element are set, the voting structure/settable memory element with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the voting structure/settable memory element. The propagation delay through the voting structure/settable memory element is the only propagation delay of the triple redundant latch.
摘要翻译： 在优选实施例中，本发明提供了一种用于更小和更快的三重冗余锁存器的电路和方法。 两个可设置的存储器元件和投票结构/可设置存储元件将相同的逻辑值设置到每个可设置的存储元件中，以及投票结构/可设置存储元件。 在可设置的存储器元件和投票结构/可设置存储元件被设置之后，具有来自第一可设定存储元件，第二存储器元件的输入和对可设置存储器元件的控制的投票结构/可设置存储元件确定保持的逻辑值 在投票结构/可设置的记忆元素上。 通过投票结构/可设置存储元件的传播延迟是三重冗余锁存器的唯一传播延迟。
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公开(公告)号：US06624482B2
公开(公告)日：2003-09-23
申请号：US10079531
申请日：2002-02-22
申请人： Jonathan P Lotz
发明人： Jonathan P Lotz
IPC分类号： H01L2976
CPC分类号： H01L29/66234 , H01L29/66772 , H01L29/78618
摘要： The present invention creates a useful BJT by increasing the gain associated with the parasitic BJT on an SOI or bulk type MOSFET. This is done by masking those manufacturing steps that minimize the BJT's beta value, by intentionally increasing the beta value of the BJT, and by driving the base of the BJT with the circuit. Once the gain is increased sufficiently, the BJT may be used productively in the circuit. Because the physical structure of the BJT is already part of the silicon water, its productive use does not require additional space.
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8.发明授权High reliability triple redundant latch with voting logic on each storage node 失效每个存储节点上具有投票逻辑的高可靠性三重冗余锁存器公开(公告)号：US07179690B2
公开(公告)日：2007-02-20
申请号：US11074526
申请日：2005-03-07
CPC分类号： H03K3/0375
摘要： In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.
摘要翻译： 在优选实施例中，本发明提供了一种用于高可靠性三重冗余锁存器的电路和方法。 三个可设置的存储器元件将相同的逻辑值设置到每个可设置的存储器元件中。 在可设置的存储器元件被设置之后，具有来自第一，第二和第三可设置存储器元件的输入的三个投票结构以及对可设置的存储器元件的控制确定保持在可设置的存储器元件上的逻辑值。 通过锁存器的传播延迟是三重冗余锁存器的唯一传播延迟。
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公开(公告)号：US07095262B2
公开(公告)日：2006-08-22
申请号：US10894720
申请日：2004-07-19
申请人： John T. Petersen , Hassan Naser , Jonathan P Lotz
发明人： John T. Petersen , Hassan Naser , Jonathan P Lotz
IPC分类号： H03K3/02
CPC分类号： H03K3/0375 , G11C11/41 , G11C29/32 , H03K3/012
摘要： In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the second settable memory element, the third settable memory element and control to the settable memory elements determine the logical value held on the first settable memory element. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.
摘要翻译： 在优选实施例中，本发明提供了具有集成可测性的高可靠性三重冗余锁存器的电路和方法。 三个可设置的存储器元件将相同的逻辑值设置到每个可设置的存储器元件中。 在可设置的存储器元件被设置之后，具有来自第二可设置存储元件，第三可设置存储器元件的输入和对可设置存储器元件的控制的投票结构确定保持在第一可设置存储器元件上的逻辑值。 数据可以被扫描进出第二可设定存储元件。 数据通过缓冲器传播到第三可设置的存储元件中。 第三可设置存储元件可用于从三重冗余锁存器中扫描数据。 通过锁存器的传播延迟是三重冗余锁存器的唯一传播延迟。
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公开(公告)号：US06584600B2
公开(公告)日：2003-06-24
申请号：US09784662
申请日：2001-02-15
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： Computer-readable media and methods for designing semiconductor artwork. Basic building blocks, or leaf cells, of an existing piece of semiconductor artwork are transferred to a new piece of semiconductor artwork in order to streamline the design process of the new design. In addition to being transferred, the position of METAL 1 layers within the leaf cells are also analyzed to avert possible design rule violations in the new design.
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