Apparatus for Controlling Slew Rate
    1.
    发明申请
    Apparatus for Controlling Slew Rate 有权
    用于控制压摆率的装置

    公开(公告)号:US20120146716A1

    公开(公告)日:2012-06-14

    申请号:US12964412

    申请日:2010-12-09

    IPC分类号: G05F1/10

    摘要: An apparatus for controlling slew rate is coupled to two adjustable voltage rails. The output of the apparatus is coupled to the gate of a switching element. By employing two adjustable voltage rails, the slew rate of the switching element is proportional to the voltage difference between the first adjustable rail and the second adjustable rail. The slew rate control apparatus can be applied to a variety of switching elements including N channel Field Effect Transistors (NFETs), P channel Field Effect Transistors (PFETs), current mode logic circuits and level shifter circuits.

    摘要翻译: 用于控制转换速率的装置耦合到两个可调电压轨。 该装置的输出耦合到开关元件的栅极。 通过采用两个可调电压轨道,开关元件的转换速率与第一可调节轨道和第二可调节轨道之间的电压差成比例。 压摆率控制装置可以应用于包括N沟道场效应晶体管(NFET),P沟道场效应晶体管(PFET),电流模式逻辑电路和电平移位器电路的各种开关元件。

    Apparatus for controlling slew rate
    2.
    发明授权
    Apparatus for controlling slew rate 有权
    用于控制转换速率的设备

    公开(公告)号:US09236856B2

    公开(公告)日:2016-01-12

    申请号:US12964412

    申请日:2010-12-09

    摘要: An apparatus for controlling slew rate is coupled to two adjustable voltage rails. The output of the apparatus is coupled to the gate of a switching element. By employing two adjustable voltage rails, the slew rate of the switching element is proportional to the voltage difference between the first adjustable rail and the second adjustable rail. The slew rate control apparatus can be applied to a variety of switching elements including N channel Field Effect Transistors (NFETs), P channel Field Effect Transistors (PFETs), current mode logic circuits and level shifter circuits.

    摘要翻译: 用于控制转换速率的装置耦合到两个可调电压轨。 该装置的输出耦合到开关元件的栅极。 通过采用两个可调电压轨道,开关元件的转换速率与第一可调节轨道和第二可调节轨道之间的电压差成比例。 压摆率控制装置可以应用于包括N沟道场效应晶体管(NFET),P沟道场效应晶体管(PFET),电流模式逻辑电路和电平移位器电路的各种开关元件。

    Level shifter design
    3.
    发明授权
    Level shifter design 有权
    电平移位器设计

    公开(公告)号:US08324955B2

    公开(公告)日:2012-12-04

    申请号:US13051343

    申请日:2011-03-18

    IPC分类号: H03L5/00

    CPC分类号: H03K19/018507 H03K3/037

    摘要: A level shifter receives an input voltage signal and produces an output voltage signal. The level shifter includes a first inverter, configured to operate at a potential difference between a first voltage V1 and a second voltage V2. The output from the invert is capacitively coupled to an input of a latch circuit via a capacitor. The capacitor has a first terminal connected to the output terminal of the first inverter, and further has a second terminal. The level shifter has a resistor connected to a third voltage V3 and to the capacitor for tying the input to the latch circuit to a desired voltage. The latch circuit is configured to operate at a potential difference between a fourth voltage V4 and a fifth voltage V5. The latch has an input node connected to the resistor and the capacitor, and further has an output node connected to an output node of the level shifter.

    摘要翻译: 电平移位器接收输入电压信号并产生输出电压信号。 电平移位器包括第一反相器,其被配置为在第一电压V1和第二电压V2之间的电位差下工作。 反相器的输出通过电容电容耦合到锁存电路的输入端。 电容器具有连接到第一反相器的输出端子的第一端子,并且还具有第二端子。 电平移位器具有连接到第三电压V3的电阻器和用于将输入端连接到锁存电路的电容器以达到期望的电压。 闩锁电路被配置为在第四电压V4和第五电压V5之间的电位差下工作。 锁存器具有连接到电阻器和电容器的输入节点,并且还具有连接到电平移位器的输出节点的输出节点。

    LDO REGULATORS FOR INTEGRATED APPLICATIONS
    4.
    发明申请
    LDO REGULATORS FOR INTEGRATED APPLICATIONS 有权
    集成应用的LDO调节器

    公开(公告)号:US20110089916A1

    公开(公告)日:2011-04-21

    申请号:US12857092

    申请日:2010-08-16

    IPC分类号: G05F1/10

    摘要: Embodiments of the invention are related to LDO regulators. In an embodiment, an amplifier drives the gate of a master source follower and of at least one slave source follower to form an LDO regulator. In an alternative embodiment, a charge pump drives the master source follower to form the regulator. Additional slave source followers may be used in conjunction with the charge pump and the master source follower to improve the regulator performance. Other embodiments are also disclosed.

    摘要翻译: 本发明的实施例涉及LDO调节器。 在一个实施例中,放大器驱动主源跟随器的栅极和至少一个从源极跟随器的栅极以形成LDO调节器。 在替代实施例中,电荷泵驱动主源极跟随器以形成调节器。 附加的从源跟随器可以与电荷泵和主源极跟随器一起使用,以改善调节器的性能。 还公开了其他实施例。

    Level Shifter Design
    6.
    发明申请
    Level Shifter Design 有权
    水平移位器设计

    公开(公告)号:US20120235728A1

    公开(公告)日:2012-09-20

    申请号:US13051343

    申请日:2011-03-18

    IPC分类号: H03L5/00

    CPC分类号: H03K19/018507 H03K3/037

    摘要: A level shifter receives an input voltage signal and produces an output voltage signal. The level shifter includes a first inverter, configured to operate at a potential difference between a first voltage V1 and a second voltage V2. The output from the invert is capacitively coupled to an input of a latch circuit via a capacitor. The capacitor has a first terminal connected to the output terminal of the first inverter, and further has a second terminal. The level shifter has a resistor connected to a third voltage V3 and to the capacitor for tying the input to the latch circuit to a desired voltage. The latch circuit is configured to operate at a potential difference between a fourth voltage V4 and a fifth voltage V5. The latch has an input node connected to the resistor and the capacitor, and further has an output node connected to an output node of the level shifter.

    摘要翻译: 电平移位器接收输入电压信号并产生输出电压信号。 电平移位器包括第一反相器,其被配置为在第一电压V1和第二电压V2之间的电位差下工作。 反相器的输出通过电容电容耦合到锁存电路的输入端。 电容器具有连接到第一反相器的输出端子的第一端子,并且还具有第二端子。 电平移位器具有连接到第三电压V3的电阻器和用于将输入端连接到锁存电路的电容器以达到期望的电压。 闩锁电路被配置为在第四电压V4和第五电压V5之间的电位差下工作。 锁存器具有连接到电阻器和电容器的输入节点,并且还具有连接到电平移位器的输出节点的输出节点。

    Noise shaping for digital pulse-width modulators
    7.
    发明授权
    Noise shaping for digital pulse-width modulators 有权
    数字脉宽调制器的噪声整形

    公开(公告)号:US09013341B2

    公开(公告)日:2015-04-21

    申请号:US13619034

    申请日:2012-09-14

    IPC分类号: H03M3/00 H03H17/00

    摘要: A circuit including an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a noise shaper. The noise shaper is configured to truncate the digital output and generate a noise shaper output having a lower number of bits than the digital output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC). The PWM DAC configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output.

    摘要翻译: 包括模数转换器(ADC)的电路。 ADC配置为接收模拟反馈信号和模拟输入信号并产生数字输出。 电路还包括噪声整形器。 噪声整形器被配置为截断数字输出并产生具有比数字输出低的位数的噪声整形器输出,并且形成在截断期间产生的量化噪声。 电路还包括脉宽调制数模转换器(PWM DAC)。 PWM DAC被配置为处理噪声整形器输出的截断数字输出并产生PWM DAC输出。

    Dynamic control loop for switching regulators
    8.
    发明授权
    Dynamic control loop for switching regulators 有权
    用于开关稳压器的动态控制回路

    公开(公告)号:US08450990B2

    公开(公告)日:2013-05-28

    申请号:US12856918

    申请日:2010-08-16

    IPC分类号: G05F1/575 G05F1/618

    摘要: A method of controlling a regulator includes turning on a first driver during a first cycle for a first time period. A second driver is turned on during the first cycle for a second time period. The first and second drivers are off during the first cycle for a third time period. The first time period is adjusted to become an adjusted first time period for a second cycle based on a ratio and a voltage difference between a peak value of the output voltage and a first voltage during the first cycle. The ratio refers to the first time period over the first time period and the second time period.

    摘要翻译: 一种控制调节器的方法包括在第一周期内第一时间段内打开第一驱动器。 第二个驱动程序在第一个周期内打开第二个时间段。 第一个和第二个驱动程序在第一个周期内关闭了第三个时间段。 基于第一周期期间输出电压的峰值和第一电压之间的比率和电压差,调整第一时间段以变为第二周期的调整后的第一时间段。 该比率是指在第一时间段和第二时间段的第一时间段。

    Noise shaping for digital pulse-width modulators
    9.
    发明授权
    Noise shaping for digital pulse-width modulators 有权
    数字脉宽调制器的噪声整形

    公开(公告)号:US08299946B2

    公开(公告)日:2012-10-30

    申请号:US12959869

    申请日:2010-12-03

    IPC分类号: H03M3/00

    摘要: A noise shaper that compares an input signal to a feedback output signal, which is a truncated version of the input signal, and generates the difference between the two signals (i.e., the error). The noise shaper then integrates the errors by adding to the error multiple of its delayed versions, and quantizes the integrated errors in such a way that the spectrum of the quantization noise is shaped toward high frequencies to be removed by a LC low-pass filter used in conjunction with the noise shaper. The low frequency content of the desired signal is mostly unaffected.

    摘要翻译: 一种噪声整形器,其将输入信号与输入信号的截断形式的反馈输出信号进行比较,并产生两个信号之间的差异(即误差)。 然后,噪声整形器通过加上其延迟版本的误差倍数来积分误差,并且量化积分误差,使得量化噪声的频谱朝向高频成形,以通过LC低通滤波器去除 结合噪音整形器。 所需信号的低频内容大部分不受影响。

    DIGITAL CONTROL OF POWER CONVERTERS
    10.
    发明申请
    DIGITAL CONTROL OF POWER CONVERTERS 有权
    电力转换器的数字控制

    公开(公告)号:US20090237966A1

    公开(公告)日:2009-09-24

    申请号:US12197790

    申请日:2008-08-25

    IPC分类号: H02M3/00

    摘要: A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, and comparing the digital error signal to at least a first threshold value. If the digital error signal is less than the first threshold value, a pulse is generated to control the power converter. Another embodiment includes multiple thresholds that may be compared against the digital error signal.

    摘要翻译: 提出了一种用于控制功率转换器的系统和方法。 实施例包括连接到模拟 - 数字转换器的模拟差分电路,并将数字误差信号与至少第一阈值进行比较。 如果数字误差信号小于第一阈值,则产生脉冲以控制功率转换器。 另一实施例包括可与数字误差信号进行比较的多个阈值。