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公开(公告)号：US11461075B2
公开(公告)日：2022-10-04
申请号：US17004228
申请日：2020-08-27
摘要： According to an embodiment, an arithmetic device includes a comparator, M cross switches, and M coefficient circuits. The comparator compares a first voltage generated at a first comparison terminal and a second voltage generated at a second comparison terminal. The M cross switches are provided corresponding to the M input signals. The M coefficient circuits are provided corresponding to the M coefficients, and each includes a first constant current source and a second constant current source. Each of the M cross switches performs switching between a straight state and a reverse state. In each of the M coefficient circuits, the first constant current source is connected between a positive output terminal of the corresponding coefficient circuit and a reference potential, and the second constant current source is connected between a negative output terminal of the corresponding coefficient circuit and the reference potential.
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公开(公告)号：US11380375B2
公开(公告)日：2022-07-05
申请号：US17185769
申请日：2021-02-25
摘要： A storage device according to an embodiment is for storing weights being continuous values. The storage device includes: a shift register, an initialization circuit, an update control circuit, and a readout control circuit. The shift resistor includes a plurality of cells, each being arranged in series and storing information. A position of each of the plurality of cells corresponds to the weight. The initialization circuit writes the information to a cell in the shift register. The update control circuit shifts a position of the cell storing the information in a direction corresponding to a sign of an update amount by a number of cells corresponding to an absolute value of the update amount. The readout control circuit reads out the information and outputs an output value according to the weight corresponding to the position of the cell storing the information.
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公开(公告)号：US10528270B2
公开(公告)日：2020-01-07
申请号：US15456209
申请日：2017-03-10
发明人： Keiko Abe , Hiroki Noguchi , Susumu Takeda , Kumiko Nomura , Shinobu Fujita
IPC分类号： G06F3/06 , G11C11/406 , G06F11/16
摘要： A memory system has a nonvolatile memory to have a memory capacity equal to or less than a memory capacity of a volatile memory, and store at least a part of data stored in the volatile memory, a first controller to refresh data in the volatile memory, and a second controller to overwrite the nonvolatile memory with data read from the volatile memory in a first period between a second period to refresh data in the volatile memory and a third period to subsequently refresh data in the volatile memory.
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公开(公告)号：US12073311B2
公开(公告)日：2024-08-27
申请号：US17005731
申请日：2020-08-28
摘要： A synaptic circuit according to an embodiment includes: a weight current circuit that applies a weight current corresponding to a weight value; an input switch that switches whether or not to cause the weight current circuit to apply the weight current; a capacitor that includes a first terminal and a second terminal, the first terminal being given a constant voltage; an output circuit that outputs the output signal corresponding to a capacitor voltage; a charge adjustment circuit that decreases or increases charges accumulated in the capacitor by drawing, from the second terminal, a capacitor current corresponding to a current value of the weight current, or supplying the capacitor current to the second terminal; and a control circuit that switches whether or not to reduce a current having a predetermined current value from the capacitor current in accordance with the weight value.
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公开(公告)号：US11651193B2
公开(公告)日：2023-05-16
申请号：US16555430
申请日：2019-08-29
发明人： Takao Marukame , Yoshifumi Nishi , Kumiko Nomura
摘要： According to an embodiment, an operation apparatus includes a first neural network, a second neural network, an evaluation circuit, and a coefficient-updating circuit. The first neural network performs an operation in a first mode. The second neural network performs an operation in a second mode and has a same layer structure as the first neural network. The evaluation circuit evaluates an error of the operation of the first neural network in the first mode and evaluates an error of the operation of the second neural network in the second mode. The coefficient-updating circuit updates, in the first mode, coefficients set for the second neural network based on an evaluating result of the error of the operation of the first neural network, and updates, in the second mode, coefficients set for the first neural network based on an evaluating result of the error of the operation of the second neural network.
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公开(公告)号：US11461617B2
公开(公告)日：2022-10-04
申请号：US15911366
申请日：2018-03-05
发明人： Kumiko Nomura , Takao Marukame
摘要： According to an embodiment, a neural network device includes a plurality of cores, and a plurality of routers. Each of the plurality of routers includes an input circuit and an output circuit. Each of the plurality of cores transmits at least one of forward direction data propagating in the neural network in a forward direction and reverse direction data propagating in the neural network in a reverse direction. The input circuit receives the forward direction data and the reverse direction data from any one of the plurality of cores and the plurality of routers. The output circuit or the input circuit selectively deletes the reverse direction data stored based on a request signal for requesting reception of data.
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公开(公告)号：US20140379975A1
公开(公告)日：2014-12-25
申请号：US14208132
申请日：2014-03-13
发明人： Kazutaka IKEGAMI , Shinobu Fujita , Keiko Abe , Kumiko Nomura , Hiroki Noguchi
IPC分类号： G11C14/00
CPC分类号： G11C14/0081 , G06F1/3228 , G06F1/3287 , G06F1/3296 , G06F12/0895 , G06F2212/225 , Y02D10/171 , Y02D10/172
摘要： According to one embodiment, a processor includes a core controlling processing data, a cache data area storing the processing data as cache data in a nonvolatile manner, a first tag area storing a tag data of the cache data in a volatile manner, a second tag area storing the tag data in a nonvolatile manner, a tag controller controlling the tag data. The tag controller determines whether the processing data is stored in the cache data area by acquiring the tag data from one of the first and second tag areas.
摘要翻译： 根据一个实施例，处理器包括核心控制处理数据，以非易失性方式存储作为高速缓存数据的处理数据的高速缓存数据区域，以易失性方式存储高速缓存数据的标签数据的第一标签区域，第二标签 以非挥发性方式存储标签数据的区域，控制标签数据的标签控制器。 标签控制器通过从第一标签区域和第二标签区域之一获取标签数据来确定处理数据是否存储在高速缓存数据区域中。
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公开(公告)号：US20130301345A1
公开(公告)日：2013-11-14
申请号：US13763068
申请日：2013-02-08
发明人： Hiroki NOGUCHI , Shinobu Fujita , Keiko Abe , Kumiko Nomura , Kazutaka Ikegami
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1659 , G11C11/1673 , G11C11/1693
摘要： According to one embodiment, a magnetic random access memory includes a write circuit to write s-bit (s is a natural number equal to 2 or greater) write data to magnetoresistive elements, and a read circuit to read s-bit read data from the magnetoresistive elements. The control circuit is configured to select one of first and second modes based on a mode selection signal, read the read data by the read circuit and write one of the write data and inversion data of the write data to the magnetoresistive elements by the write circuit based on the read data and the write data if free space of the buffer memory is equal to a fixed value or more when the second mode is selected.
摘要翻译： 根据一个实施例，磁性随机存取存储器包括写入电路以将写入数据写入磁阻元件的s位（s是等于2或更大的自然数）写入数据;以及读取电路，用于从 磁阻元件。 控制电路被配置为基于模式选择信号选择第一和第二模式之一，通过读取电路读取读取的数据，并且通过写入电路将写入数据的写入数据和反相数据写入磁阻元件中 如果选择第二模式，则缓冲存储器的可用空间等于固定值或更大值时，基于读取数据和写入数据。
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公开(公告)号：US11625579B2
公开(公告)日：2023-04-11
申请号：US16803641
申请日：2020-02-27
发明人： Yoshifumi Nishi , Kumiko Nomura , Radu Berdan , Takao Marukame
摘要： A spiking neural network device according to an embodiment includes a synaptic element, a neuron circuit, a synaptic potentiator, and a synaptic depressor. The synaptic element has a variable weight. The neuron circuit inputs a spike voltage having a magnitude adjusted in accordance with the weight of the synaptic element via the synaptic element, and fires when a predetermined condition is satisfied. The synaptic potentiator performs a potentiating operation for potentiating the weight of the synaptic element depending on input timing of the spike voltage and firing timing of the neuron circuit. The synaptic depressor performs a depression operation for depressing the weight of the synaptic element in accordance with a schedule independent from the input timing of the spike voltage and the firing timing of the neuron circuit.
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公开(公告)号：US11620501B2
公开(公告)日：2023-04-04
申请号：US16564344
申请日：2019-09-09
发明人： Kumiko Nomura , Takao Marukame , Yoshifumi Nishi
IPC分类号： G06N3/063 , G06N3/04 , G06F16/901
摘要： According to an embodiment, a neural network apparatus includes cores, routers, a tree path, and a short-cut path. The cores are provided according to leaves in a tree structure, each core serving as a circuit that performs calculation or processing for part of elements of the neural network. The routers are provided according to nodes other than the leaves in the tree structure. The tree path connects the cores and the routers such that data is transferred along the tree structure. The short-cut path connects part of the routers such that data is transferred on a route differing from the tree path. The routers transmit data output from each core to any of the cores serving as a transmission destination on one of routes in the tree path and the short-cut path such that the calculation or the processing is performed according to a structure of the neural network.
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