公开(公告)号：US20240049463A1

公开(公告)日：2024-02-08

申请号：US18487546

申请日：2023-10-16

申请人： KEY FOUNDRY CO., LTD.

发明人： Su Jin KIM ,  Min Kuck CHO ,  Jung Hwan LEE ,  In Chul JUNG

IPC分类号： H10B41/35 ,  H01L29/66 ,  H01L29/788

CPC分类号： H10B41/35 ,  H01L29/66825 ,  H01L29/7883

摘要： A single poly non-volatile memory device is provided. The single poly non-volatile memory device is formed in a semiconductor substrate, and includes a sensing transistor, a selection transistor, and a capacitor, wherein a thickness of a selection gate insulating film is formed to be thicker than a thickness of a sensing gate insulating film, wherein a thickness of a control gate insulating film of the capacitor is formed to be the same, or greater than, a thickness of the sensing gate insulating film, and wherein the sensing gate of the sensing transistor and the control gate of the capacitor are physically and electrically connected to each other.

公开(公告)号：US20220406802A1

公开(公告)日：2022-12-22

申请号：US17560627

申请日：2021-12-23

申请人： KEY FOUNDRY CO., LTD.

发明人： Jin Shik CHOI ,  Su Jin KIM ,  Won Kyu LIM

IPC分类号： H01L27/11529 ,  H01L27/11519 ,  H01L27/11548

摘要： A non-volatile memory device, includes a source region and a drain region disposed in a channel length direction on a substrate; a flash cell, including a floating gate and a control gate, disposed between the source region and the drain region; a selection gate disposed between the source region and the flash cell; a selection line connecting the selection gate; a word line connecting the control gate; a common source line connected to the source region; and a bit line connected to the drain region.

公开(公告)号：US20230059628A1

公开(公告)日：2023-02-23

申请号：US17743691

申请日：2022-05-13

申请人： KEY FOUNDRY CO., LTD.

发明人： Su Jin KIM ,  Min Kuck CHO ,  Jung Hwan LEE ,  In Chul JUNG

IPC分类号： H01L27/11531 ,  H01L29/423

摘要： A semiconductor device includes: a logic region and a non-volatile memory (NVM) region; a logic gate insulating film disposed on a substrate in the logic region; at least one gate oxidation acceleration ion implantation layer disposed in the NVM region; at least one NVM gate insulating film disposed on the at least one gate oxidation acceleration ion implantation layer; a logic gate electrode disposed on the logic gate insulating film; and at least one NVM gate electrode disposed on the at least one NVM gate insulating film, wherein a thickness of the at least one NVM gate insulating film is equal or greater than a thickness of the logic gate insulating film.

公开(公告)号：US20230053444A1

公开(公告)日：2023-02-23

申请号：US17564367

申请日：2021-12-29

申请人： KEY FOUNDRY CO., LTD.

发明人： Su Jin KIM ,  Min Kuck CHO ,  Jung Hwan LEE ,  In Chul JUNG

IPC分类号： H01L27/11524 ,  H01L29/788 ,  H01L29/66

摘要： A single poly non-volatile memory device is provided. The single poly non-volatile memory device is formed in a semiconductor substrate, and includes a sensing transistor, a selection transistor, and a capacitor, wherein a thickness of a selection gate insulating film is formed to be thicker than a thickness of a sensing gate insulating film, wherein a thickness of a control gate insulating film of the capacitor is formed to be the same, or greater than, a thickness of the sensing gate insulating film, and wherein the sensing gate of the sensing transistor and the control gate of the capacitor are physically and electrically connected to each other.

公开(公告)号：US20210082938A1

公开(公告)日：2021-03-18

申请号：US17108444

申请日：2020-12-01

申请人： Key Foundry Co., Ltd.

发明人： Su Jin KIM ,  Hye Jin YOO

IPC分类号： H01L27/11558 ,  H01L27/11524 ,  H01L29/788 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

摘要： A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.

公开(公告)号：US20220384472A1

公开(公告)日：2022-12-01

申请号：US17531873

申请日：2021-11-22

申请人： KEY FOUNDRY CO., LTD.

发明人： Su Jin KIM

IPC分类号： H01L27/11558 ,  H01L27/11536 ,  H01L27/11541 ,  H01L27/11543

摘要： A semiconductor device includes a single poly non-volatile memory device including a sensing and selection gate structure, an erase gate structure, and a control gate structure. The sensing and selection gate structure includes a sensing gate and a selection gate, a bit line, a word line disposed on the selection gate, and a tunneling gate line. The erase gate structure includes an erase gate, and an erase gate line disposed near the erase gate. The control gate structure includes a control gate disposed on the substrate, and a control gate line disposed near the control gate. The sensing gate, the selection gate, the erase gate and the control gate are connected by one conductive layer. The erase gate structure implements a PMOS capacitor, an NMOS transistor, or a PMOS transistor. The semiconductor device includes a single poly non-volatile memory device including a separate program area and erase area.