公开(公告)号：US11990406B2

公开(公告)日：2024-05-21

申请号：US17860345

申请日：2022-07-08

Applicant: KIOXIA CORPORATION

Inventor： Kosuke Yanagidaira ,  Chikaaki Kodama

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L27/02 ,  H10B41/10 ,  H10B41/40 ,  H10B41/41

CPC classification number: H01L23/528 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/522 ,  H01L27/0207 ,  H10B41/10 ,  H10B41/40 ,  H10B41/41 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

公开(公告)号：US11417600B2

公开(公告)日：2022-08-16

申请号：US17079952

申请日：2020-10-26

Applicant: KIOXIA CORPORATION

Inventor： Kosuke Yanagidaira ,  Chikaaki Kodama

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/02 ,  H01L23/48

Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.