SEMICONDUCTOR STORAGE DEVICE
    1.
    发明申请

    公开(公告)号:US20220093149A1

    公开(公告)日:2022-03-24

    申请号:US17189097

    申请日:2021-03-01

    Abstract: A semiconductor storage device includes a plurality of gate electrodes, a semiconductor layer facing the plurality of gate electrodes, a gate insulating layer arranged between each of the plurality of gate electrodes and the semiconductor layer. The gate insulating layer contains oxygen (O) and hafnium (Hf) and has an orthorhombic crystal structure. A plurality of first wirings is connected to the respective gate electrodes. A controller is configured to execute a write sequence and an erasing sequence by applying certain voltages to at least one of the first wirings. The controller is further configured to increase either a program voltage to be applied to the first wirings in the write sequence or an application time of the program voltage in the write sequence after a total number of executions of the write sequence or the erasing sequence has reached a particular number.

    MEMORY DEVICE
    2.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号:US20240298450A1

    公开(公告)日:2024-09-05

    申请号:US18588621

    申请日:2024-02-27

    Abstract: A memory device includes: a first electrode layer extending in a first direction intersecting a surface of a substrate; a second electrode layer extending in the first direction; a first conductive layer surrounding the first electrode layer and the second electrode layer; a first insulating layer between the first electrode layer and the first conductive layer, surrounding the first electrode layer, and including hafnium oxide and/or zirconium oxide; a second insulating layer between the second electrode layer and the first conductive layer, surrounding the second electrode layer, and including hafnium oxide and/or zirconium oxide; a first gate electrode layer extending in the first direction, a first semiconductor layer surrounding the first gate electrode layer and electrically connected to the first conductive layer; and a first gate insulating layer between the first gate electrode layer and the first semiconductor layer and surrounding the first gate electrode layer.

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