公开(公告)号：US20230142767A1

公开(公告)日：2023-05-11

申请号：US17903636

申请日：2022-09-06

Applicant: Kioxia Corporation

Inventor： Keiri NAKANISHI ,  Kensaku YAMAGUCHI ,  Takashi TAKEMOTO

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to one embodiment, a controller of a memory system manages a first table maintaining a relationship between a logical address and a physical address, compresses first data corresponding to a first address of a write command, specifies a size of second data obtained by compressing the first data, determines allocation of the second data on a memory based on the size of the second data, stores a second address corresponding to a physical area where a head of the second data is stored and a physical area number used to store the second data in an entry of the first logical address in the first table, and stores the first address, offset of a position of a leader of the second data in the physical area, and the size of the second data in the physical area.

公开(公告)号：US20240241644A1

公开(公告)日：2024-07-18

申请号：US18619262

申请日：2024-03-28

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO ,  Kensaku YAMAGUCHI ,  Takehiko KURASHIGE ,  Yuki SASAKI

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to one embodiment, in response to receiving, from a host, one or more second type commands, a controller of the storage device maintains the received one or more second type commands in a memory region in the storage device without completing processing of the received one or more second type commands. In response to receiving the first type command from the host, the controller completes processing of a second type command, and transmits a command completion response for the first type command to the host as a first preceding response for the first type command. In response to completion of processing of the first type command, the controller transmits a command completion response for the first type command to the host.

公开(公告)号：US20230236730A1

公开(公告)日：2023-07-27

申请号：US17931363

申请日：2022-09-12

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO ,  Kensaku YAMAGUCHI ,  Takehiko KURASHIGE ,  Yuki SASAKI

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0679 ,  G06F3/0659

Abstract: According to one embodiment, in response to receiving, from a host, one or more second type commands, a controller of the storage device maintains the received one or more second type commands in a memory region in the storage device without completing processing of the received one or more second type commands. In response to receiving the first type command from the host, the controller completes processing of a second type command, and transmits a command completion response for the first type command to the host as a first preceding response for the first type command. In response to completion of processing of the first type command, the controller transmits a command completion response for the first type command to the host.

公开(公告)号：US20240303188A1

公开(公告)日：2024-09-12

申请号：US18593215

申请日：2024-03-01

Applicant: Kioxia Corporation

Inventor： Takashi TAKEMOTO ,  Kensaku YAMAGUCHI ,  Keiri NAKANISHI ,  Kohei OIKAWA ,  Sho KODAMA

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0253 ,  G06F2212/7201

Abstract: A memory system includes a nonvolatile memory and a controller. The controller is configured to maintain an address mapping table including first mapping information indicating correspondence between logical addresses and physical addresses of the nonvolatile memory in units of physical regions each having a predetermined size. The controller, during a write operation compresses write data of the predetermined size into a compressed write data, determines a physical address range in which the compressed write data is to be written, writes the compressed write data into the physical address range and also second mapping information into an area in one or more physical regions spanned by the physical address range, and updates the address mapping table. The second mapping information indicates a logical address of the write data, an information capable of specifying an offset, and a size of the compressed write data.

公开(公告)号：US20230305718A1

公开(公告)日：2023-09-28

申请号：US17899398

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Takashi TAKEMOTO ,  Kensaku YAMAGUCHI

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0658 ,  G06F3/0679

Abstract: A memory system includes a nonvolatile memory and a controller. The controller is configured to segment data into clusters, perform a compression with respect to each of the clusters, allocate the clusters subjected to the compression to encoding frames in accordance with a predetermined rule. According to the predetermined rule, at least a part of a cluster is allocated to a vacant space of an encoding frame in a first state, when a predetermined condition is met, and an entirety of a cluster is allocated to an encoding frame in a second state, when no encoding frame in the first state exists or when the predetermined condition is not met. The controller is further configured to encode data in each of the encoding frames and write the encoded data into the nonvolatile memory.

公开(公告)号：US20250094345A1

公开(公告)日：2025-03-20

申请号：US18821905

申请日：2024-08-30

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO ,  Yuki SASAKI ,  Kensaku YAMAGUCHI

IPC: G06F12/02

Abstract: A memory system includes a non-volatile memory and a controller that is configured to: write N pieces of address translation information repeatedly in a first block according to a first order; write the N pieces of address translation information repeatedly in a second block of the non-volatile memory according to a second order that is offset from the first order by N/2; write an update log in the first and second blocks each time one of the N pieces is written; and in response to power to the memory system being restored after shutdown, read from the first block, N/2 pieces of address translation information and N/2 update logs last written thereinto, read from the second block, N/2 pieces of address translation information and N/2 update logs last written thereinto, and reconstruct a logical-to-physical address translation table from the information read from the non-volatile memory.

公开(公告)号：US20240094940A1

公开(公告)日：2024-03-21

申请号：US18460284

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Kensaku YAMAGUCHI ,  Kiyotaka IWASAKI ,  Takashi TAKEMOTO ,  Kohei OIKAWA

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0608 ,  G06F3/0679

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform a write operation of a first data cluster and a first partial overwrite operation of the first data cluster with first overwrite data. The write operation includes compressing and then encrypting the first data cluster, and writing the compressed and encrypted first data cluster into a first physical location of the non-volatile memory. The first partial overwrite operation includes encrypting the first overwrite data without performing compression, reading the compressed and encrypted first data cluster from the first physical location of the non-volatile memory, generating a first composite data cluster with the compressed and encrypted first data cluster read from the first physical location and the encrypted first overwrite data that is not compressed, and writing the first composite data cluster into a second physical location of the non-volatile memory.

公开(公告)号：US20210081327A1

公开(公告)日：2021-03-18

申请号：US16805946

申请日：2020-03-02

Applicant: Kioxia Corporation

Inventor： Kensaku YAMAGUCHI ,  Shinichi KANNO

IPC: G06F12/1009

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a movement request from a host, the movement request designating a logical address of movement target data. When update data corresponding to the designated logical address is not written to the nonvolatile memory by a write request from the host in a period from the reception of the movement request to start of movement of data corresponding to the designated logical address, the controller executes a movement process of moving data corresponding to the designated logical address to a movement destination block in the nonvolatile memory. When the update data is written to the nonvolatile memory in the period, the controller does not execute the movement process.