公开(公告)号：US11756918B2

公开(公告)日：2023-09-12

申请号：US17184511

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Tsutomu Sano ,  Kazuya Maruyama ,  Satoru Takaku ,  Nobuhito Suzuya

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L24/46 ,  H01L24/06 ,  H01L25/0657 ,  H01L2224/06515 ,  H01L2224/46 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2924/1435

Abstract: A semiconductor device includes a first terminal, a second terminal, and a plurality of third terminals on a substrate. Memory chips are stacked on the substrate in an offset manner. Each memory chip has first pads, second pads, and third pads thereon. A first bonding wire is electrically connected to the first terminal and physically connected to a first pad of each memory chip. A second bonding wire is electrically connected to the second terminal and physically connected to a second pad of each memory chip. A third bonding wire electrically connects one third terminal to a third pad on each memory chip. A fourth bonding wire is connected to the first bonding wire at a first pad on a first memory chip of the stack and another first pad on the first memory chip. The fourth bonding wire straddles over the second bonding wire and the third bonding wire.