公开(公告)号：US12002777B2

公开(公告)日：2024-06-04

申请号：US17461550

申请日：2021-08-30

Applicant: KIOXIA CORPORATION

Inventor： Kotaro Fujii ,  Shinya Watanabe

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05149 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: According to one or more embodiments, a semiconductor device includes a first substrate and a second substrate. The first substrate includes a first metal layer and a first insulating layer. The first insulating layer surrounds the first metal layer. The second substrate includes a second metal layer, a second insulating layer, and a first conducive body. The second metal layer is in contact with the first metal layer. The second insulating layer surrounds the second metal layer and is in contact with the first insulating layer. A part of the first conductive body is in the second metal layer and extends in a first direction toward the first metal layer.

公开(公告)号：US11756909B2

公开(公告)日：2023-09-12

申请号：US17203990

申请日：2021-03-17

Applicant: Kioxia Corporation

Inventor： Shinya Watanabe ,  Shinya Arai

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: According to one embodiment, a semiconductor storage device includes a first chip and a second chip. The first chip includes a first substrate, a transistor, and a first pad. The second chip includes a second pad, a memory cell array, and a second substrate. The second pad is on the first pad. The second chip is bonded to the first chip. The first chip and the second chip includes, when viewed in a first direction orthogonal to the first substrate, a first region and a second region. The first region includes the memory cell array. The second region surrounds an area around the first region and includes a wall extending from the first substrate to the second substrate. The second substrate includes a first opening passing through the second substrate in the second region.